Prettify files

3 files changed, 11 insertions, 0 deletions

diff --git a/src/VeriFuzz/Verilog/AST.hs b/src/VeriFuzz/Verilog/AST.hs
index f940281..1b2cb19 100644
--- a/src/VeriFuzz/Verilog/AST.hs
+++ b/src/VeriFuzz/Verilog/AST.hs
@@ -144,6 +144,8 @@ instance QC.Arbitrary Delay where
 data Event = EId Identifier
            | EExpr Expr
            | EAll
+           | EPosEdge Identifier
+           | ENegEdge Identifier
            deriving (Eq, Show)
 
 instance QC.Arbitrary Event where
diff --git a/src/VeriFuzz/Verilog/CodeGen.hs b/src/VeriFuzz/Verilog/CodeGen.hs
index 58b1d16..0b7f422 100644
--- a/src/VeriFuzz/Verilog/CodeGen.hs
+++ b/src/VeriFuzz/Verilog/CodeGen.hs
@@ -155,6 +155,8 @@ genEvent :: Event -> Text
 genEvent (EId   i   ) = "@(" <> i ^. getIdentifier <> ")"
 genEvent (EExpr expr) = "@(" <> genExpr expr <> ")"
 genEvent EAll         = "@*"
+genEvent (EPosEdge i) = "@(posedge " <> i ^. getIdentifier <> ")"
+genEvent (ENegEdge i) = "@(negedge " <> i ^. getIdentifier <> ")"
 
 -- | Generates verilog code for a 'Delay'.
 genDelay :: Delay -> Text
diff --git a/src/VeriFuzz/Verilog/Mutate.hs b/src/VeriFuzz/Verilog/Mutate.hs
index dca0dd9..0e68419 100644
--- a/src/VeriFuzz/Verilog/Mutate.hs
+++ b/src/VeriFuzz/Verilog/Mutate.hs
@@ -136,3 +136,10 @@ makeTop i m = ModDecl (m ^. modId) ys (m ^. modInPorts) modIt
   ys    = Port Wire 90 . flip makeIdFrom "y" <$> [1 .. i]
   modIt = instantiateMod_ . modN <$> [1 .. i]
   modN n = m & modId %~ makeIdFrom n & modOutPorts .~ [Port Wire 90 (makeIdFrom n "y")]
+
+makeTopAssert :: ModDecl -> ModDecl
+makeTopAssert = (modItems %~ (++ [assert])) . (modInPorts %~ ((Port Wire 1 "clk") :)) . makeTop 2
+ where
+  assert = Always . EventCtrl e . Just $ SeqBlock
+    [TaskEnable $ Task "assert" [BinOp (Id "y_1") BinEq (Id "y_2")]]
+  e = EPosEdge "clk"