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author | Yann Herklotz <git@yannherklotz.com> | 2019-08-07 01:54:31 +0200 |
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committer | Yann Herklotz <git@yannherklotz.com> | 2019-08-07 01:54:31 +0200 |
commit | 54379325b98f0bce95426a80c3916b3657ad64ac (patch) | |
tree | 71ed54e657a38cd38a76f8c17a65cdc529c5b882 /src/VeriFuzz/Verilog | |
parent | a54a9a05a70f43d0a442bae24809f9b4053ac549 (diff) | |
download | verismith-54379325b98f0bce95426a80c3916b3657ad64ac.tar.gz verismith-54379325b98f0bce95426a80c3916b3657ad64ac.zip |
Add PortInfo for nondeterminism information
Diffstat (limited to 'src/VeriFuzz/Verilog')
-rw-r--r-- | src/VeriFuzz/Verilog/Mutate.hs | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/src/VeriFuzz/Verilog/Mutate.hs b/src/VeriFuzz/Verilog/Mutate.hs index 37d3a7d..2e88859 100644 --- a/src/VeriFuzz/Verilog/Mutate.hs +++ b/src/VeriFuzz/Verilog/Mutate.hs @@ -36,7 +36,6 @@ module VeriFuzz.Verilog.Mutate , combineAssigns , combineAssigns_ , declareMod - , fromPort ) where @@ -396,6 +395,3 @@ combineAssigns_ comb p ps = <$> ps ^.. traverse . portName - -fromPort :: Port -> Identifier -fromPort (Port _ _ _ i) = i |