Add hlint changes

3 files changed, 3 insertions, 4 deletions

diff --git a/src/VeriFuzz/Verilog/AST.hs b/src/VeriFuzz/Verilog/AST.hs
index dd61f03..9db4999 100644
--- a/src/VeriFuzz/Verilog/AST.hs
+++ b/src/VeriFuzz/Verilog/AST.hs
@@ -514,8 +514,7 @@ modPortGen = QC.oneof
   ]
 
 instance QC.Arbitrary ModDecl where
-  arbitrary = ModDecl <$> QC.arbitrary <*> QC.arbitrary
-              <*> QC.listOf1 modPortGen <*> QC.arbitrary
+  arbitrary = ModDecl <$> QC.arbitrary <*> QC.arbitrary <*> QC.listOf1 modPortGen <*> QC.arbitrary
 
 -- | Description of the Verilog module.
 newtype Description = Description { _getDescription :: ModDecl }
diff --git a/src/VeriFuzz/Verilog/CodeGen.hs b/src/VeriFuzz/Verilog/CodeGen.hs
index 34194a6..1551c1d 100644
--- a/src/VeriFuzz/Verilog/CodeGen.hs
+++ b/src/VeriFuzz/Verilog/CodeGen.hs
@@ -91,7 +91,7 @@ genModuleItem (ModInst (Identifier i) (Identifier name) conn) =
   i <> " " <> name <> "(" <> comma (genExpr . _modConn <$> conn) <> ")" <> ";\n"
 genModuleItem (Initial stat ) = "initial " <> genStmnt stat
 genModuleItem (Always  stat ) = "always " <> genStmnt stat
-genModuleItem (Decl dir port) = (maybe "" makePort dir) <> genPort port <> ";\n"
+genModuleItem (Decl dir port) = maybe "" makePort dir <> genPort port <> ";\n"
   where makePort = (<> " ") . genPortDir
 
 -- | Generate continuous assignment
diff --git a/src/VeriFuzz/Verilog/Mutate.hs b/src/VeriFuzz/Verilog/Mutate.hs
index 9f22faa..3052598 100644
--- a/src/VeriFuzz/Verilog/Mutate.hs
+++ b/src/VeriFuzz/Verilog/Mutate.hs
@@ -135,6 +135,6 @@ makeIdFrom a i = (i <>) . Identifier . ("_" <>) $ showT a
 makeTop :: Int -> ModDecl -> ModDecl
 makeTop i m = ModDecl (m ^. moduleId) ys (m ^. modInPorts) modIt
  where
-  ys    = Port Wire 90 . (flip makeIdFrom) "y" <$> [1 .. i]
+  ys    = Port Wire 90 . flip makeIdFrom "y" <$> [1 .. i]
   modIt = instantiateMod_ . modN <$> [1 .. i]
   modN n = m & moduleId %~ makeIdFrom n & modOutPorts .~ [Port Wire 90 (makeIdFrom n "y")]