diff options
author | Yann Herklotz Grave <git@yannherklotzgrave.com> | 2019-02-17 12:37:46 +0000 |
---|---|---|
committer | Yann Herklotz Grave <git@yannherklotzgrave.com> | 2019-02-17 12:37:46 +0000 |
commit | 928a54419aeac611555b3c15493db00010cbb46e (patch) | |
tree | 576f1ca4ba287f03700b9526032126302c0474c1 /src/VeriFuzz/Yosys.hs | |
parent | 0ea6e208f2c3c41922f8334174fc8e81a21d67f4 (diff) | |
download | verismith-928a54419aeac611555b3c15493db00010cbb46e.tar.gz verismith-928a54419aeac611555b3c15493db00010cbb46e.zip |
Indent by 4
Diffstat (limited to 'src/VeriFuzz/Yosys.hs')
-rw-r--r-- | src/VeriFuzz/Yosys.hs | 67 |
1 files changed, 34 insertions, 33 deletions
diff --git a/src/VeriFuzz/Yosys.hs b/src/VeriFuzz/Yosys.hs index 9d3a298..240cc8f 100644 --- a/src/VeriFuzz/Yosys.hs +++ b/src/VeriFuzz/Yosys.hs @@ -35,25 +35,26 @@ defaultYosys :: Yosys defaultYosys = Yosys "yosys" writeSimFile - :: Yosys -- ^ Simulator instance - -> ModDecl -- ^ Current module - -> FilePath -- ^ Output sim file - -> Sh () + :: Yosys -- ^ Simulator instance + -> ModDecl -- ^ Current module + -> FilePath -- ^ Output sim file + -> Sh () writeSimFile _ m file = do - writefile "rtl.v" $ genSource m - writefile file yosysSimConfig + writefile "rtl.v" $ genSource m + writefile file yosysSimConfig runSynthYosys :: Yosys -> ModDecl -> FilePath -> Sh () runSynthYosys sim m outf = do - dir <- pwd - writefile inpf $ genSource m - echoP "Yosys: synthesis" - _ <- logger dir "yosys" $ timeout (yosysPath sim) ["-b", "verilog -noattr", "-o", out, "-S", inp] - echoP "Yosys: synthesis done" - where - inpf = "rtl.v" - inp = toTextIgnore inpf - out = toTextIgnore outf + dir <- pwd + writefile inpf $ genSource m + echoP "Yosys: synthesis" + _ <- logger dir "yosys" + $ timeout (yosysPath sim) ["-b", "verilog -noattr", "-o", out, "-S", inp] + echoP "Yosys: synthesis done" + where + inpf = "rtl.v" + inp = toTextIgnore inpf + out = toTextIgnore outf -- ids = T.intercalate "," $ allVars m ^.. traverse . getIdentifier runMaybeSynth :: (Synthesize a) => Maybe a -> ModDecl -> Sh () @@ -62,24 +63,24 @@ runMaybeSynth Nothing m = writefile "syn_rtl.v" $ genSource m runEquivYosys :: (Synthesize a, Synthesize b) => Yosys -> a -> Maybe b -> ModDecl -> Sh () runEquivYosys yosys sim1 sim2 m = do - writefile "top.v" . genSource . initMod $ makeTop 2 m - writefile checkFile $ yosysSatConfig sim1 sim2 m - runSynth sim1 m $ fromText [st|syn_#{toText sim1}.v|] - runMaybeSynth sim2 m - echoP "Yosys: equivalence check" - run_ (yosysPath yosys) [toTextIgnore checkFile] - echoP "Yosys: equivalence done" - where checkFile = fromText [st|test.#{toText sim1}.#{maybe "rtl" toText sim2}.ys|] + writefile "top.v" . genSource . initMod $ makeTop 2 m + writefile checkFile $ yosysSatConfig sim1 sim2 m + runSynth sim1 m $ fromText [st|syn_#{toText sim1}.v|] + runMaybeSynth sim2 m + echoP "Yosys: equivalence check" + run_ (yosysPath yosys) [toTextIgnore checkFile] + echoP "Yosys: equivalence done" + where checkFile = fromText [st|test.#{toText sim1}.#{maybe "rtl" toText sim2}.ys|] runEquiv :: (Synthesize a, Synthesize b) => Yosys -> a -> Maybe b -> ModDecl -> Sh () runEquiv _ sim1 sim2 m = do - root <- rootPath - dir <- pwd - echoP "SymbiYosys: setup" - writefile "top.v" . genSource . initMod $ makeTopAssert m - writefile "test.sby" $ sbyConfig root sim1 sim2 m - runSynth sim1 m $ fromText [st|syn_#{toText sim1}.v|] - runMaybeSynth sim2 m - echoP "SymbiYosys: run" - _ <- logger dir "symbiyosys" $ run "sby" ["test.sby"] - echoP "SymbiYosys: done" + root <- rootPath + dir <- pwd + echoP "SymbiYosys: setup" + writefile "top.v" . genSource . initMod $ makeTopAssert m + writefile "test.sby" $ sbyConfig root sim1 sim2 m + runSynth sim1 m $ fromText [st|syn_#{toText sim1}.v|] + runMaybeSynth sim2 m + echoP "SymbiYosys: run" + _ <- logger dir "symbiyosys" $ run "sby" ["test.sby"] + echoP "SymbiYosys: done" |