Rename Stmnt to Statement

3 files changed, 37 insertions, 37 deletions

diff --git a/src/VeriFuzz/AST.hs b/src/VeriFuzz/AST.hs
index d37b053..e0c74a1 100644
--- a/src/VeriFuzz/AST.hs
+++ b/src/VeriFuzz/AST.hs
@@ -83,7 +83,7 @@ module VeriFuzz.AST
     , contAssignNetLVal
     , contAssignExpr
     -- * Statment
-    , Stmnt(..)
+    , Statement(..)
     , statDelay
     , statDStat
     , statEvent
@@ -476,32 +476,32 @@ instance QC.Arbitrary ContAssign where
   arbitrary = ContAssign <$> QC.arbitrary <*> QC.arbitrary
 
 -- | Statements in Verilog.
-data Stmnt = TimeCtrl       { _statDelay :: {-# UNPACK #-} !Delay
-                            , _statDStat :: Maybe Stmnt
-                            }                                -- ^ Time control (@#NUM@)
-           | EventCtrl      { _statEvent :: !Event
-                            , _statEStat :: Maybe Stmnt
-                            }
-           | SeqBlock       { _statements   :: [Stmnt] }     -- ^ Sequential block (@begin ... end@)
-           | BlockAssign    { _stmntBA      :: !Assign }     -- ^ blocking assignment (@=@)
+data Statement = TimeCtrl { _statDelay :: {-# UNPACK #-} !Delay
+                          , _statDStat :: Maybe Statement
+                          }                                -- ^ Time control (@#NUM@)
+           | EventCtrl { _statEvent :: !Event
+                       , _statEStat :: Maybe Statement
+                       }
+           | SeqBlock { _statements   :: [Statement] }     -- ^ Sequential block (@begin ... end@)
+           | BlockAssign { _stmntBA      :: !Assign }     -- ^ blocking assignment (@=@)
            | NonBlockAssign { _stmntNBA     :: !Assign }     -- ^ Non blocking assignment (@<=@)
-           | StatCA         { _stmntCA      :: !ContAssign } -- ^ Stmnt continuous assignment. May not be correct.
-           | TaskEnable     { _stmntTask    :: !Task }
-           | SysTaskEnable  { _stmntSysTask :: !Task }
+           | StatCA { _stmntCA      :: !ContAssign } -- ^ Statement continuous assignment. May not be correct.
+           | TaskEnable { _stmntTask    :: !Task }
+           | SysTaskEnable { _stmntSysTask :: !Task }
            deriving (Eq, Show, Ord, Data)
 
-makeLenses ''Stmnt
+makeLenses ''Statement
 
-instance Semigroup Stmnt where
+instance Semigroup Statement where
   (SeqBlock a) <> (SeqBlock b) = SeqBlock $ a <> b
   (SeqBlock a) <> b = SeqBlock $ a <> [b]
   a <> (SeqBlock b) = SeqBlock $ a : b
   a <> b = SeqBlock [a, b]
 
-instance Monoid Stmnt where
+instance Monoid Statement where
   mempty = SeqBlock []
 
-statement :: Int -> QC.Gen Stmnt
+statement :: Int -> QC.Gen Statement
 statement n
     | n == 0 = QC.oneof
         [ BlockAssign <$> QC.arbitrary
@@ -522,7 +522,7 @@ statement n
     | otherwise = statement 0
     where substat y = statement (n `div` y)
 
-instance QC.Arbitrary Stmnt where
+instance QC.Arbitrary Statement where
   arbitrary = QC.sized statement
 
 -- | Module item which is the body of the module expression.
@@ -531,8 +531,8 @@ data ModItem = ModCA { _modContAssign :: !ContAssign }
                        , _modInstName  :: {-# UNPACK #-} !Identifier
                        , _modInstConns :: [ModConn]
                        }
-             | Initial !Stmnt
-             | Always !Stmnt
+             | Initial !Statement
+             | Always !Statement
              | Decl { _declDir  :: !(Maybe PortDir)
                     , _declPort :: !Port
                     }
diff --git a/src/VeriFuzz/CodeGen.hs b/src/VeriFuzz/CodeGen.hs
index 3a74d94..fa0530b 100644
--- a/src/VeriFuzz/CodeGen.hs
+++ b/src/VeriFuzz/CodeGen.hs
@@ -37,10 +37,10 @@ import           VeriFuzz.Internal
 class Source a where
   genSource :: a -> Text
 
--- | Map a 'Maybe Stmnt' to 'Text'. If it is 'Just stmnt', the generated
+-- | Map a 'Maybe Statement' to 'Text'. If it is 'Just statement', the generated
 -- statements are returned. If it is 'Nothing', then @;\n@ is returned.
-defMap :: Maybe Stmnt -> Text
-defMap = maybe ";\n" genStmnt
+defMap :: Maybe Statement -> Text
+defMap = maybe ";\n" genStatement
 
 -- | Convert the 'VerilogSrc' type to 'Text' so that it can be rendered.
 genVerilogSrc :: VerilogSrc -> Text
@@ -99,8 +99,8 @@ genModuleItem :: ModItem -> Text
 genModuleItem (ModCA ca) = genContAssign ca
 genModuleItem (ModInst (Identifier i) (Identifier name) conn) =
     i <> " " <> name <> "(" <> comma (genModConn <$> conn) <> ")" <> ";\n"
-genModuleItem (Initial stat ) = "initial " <> genStmnt stat
-genModuleItem (Always  stat ) = "always " <> genStmnt stat
+genModuleItem (Initial stat ) = "initial " <> genStatement stat
+genModuleItem (Always  stat ) = "always " <> genStatement stat
 genModuleItem (Decl dir port) = maybe "" makePort dir <> genPort port <> ";\n"
     where makePort = (<> " ") . genPortDir
 
@@ -217,15 +217,15 @@ genAssign :: Text -> Assign -> Text
 genAssign op (Assign r d e) =
     genLVal r <> op <> maybe "" genDelay d <> genExpr e
 
-genStmnt :: Stmnt -> Text
-genStmnt (TimeCtrl  d stat   ) = genDelay d <> " " <> defMap stat
-genStmnt (EventCtrl e stat   ) = genEvent e <> " " <> defMap stat
-genStmnt (SeqBlock       s   ) = "begin\n" <> fold (genStmnt <$> s) <> "end\n"
-genStmnt (BlockAssign    a   ) = genAssign " = " a <> ";\n"
-genStmnt (NonBlockAssign a   ) = genAssign " <= " a <> ";\n"
-genStmnt (StatCA         a   ) = genContAssign a
-genStmnt (TaskEnable     task) = genTask task <> ";\n"
-genStmnt (SysTaskEnable  task) = "$" <> genTask task <> ";\n"
+genStatement :: Statement -> Text
+genStatement (TimeCtrl  d stat   ) = genDelay d <> " " <> defMap stat
+genStatement (EventCtrl e stat   ) = genEvent e <> " " <> defMap stat
+genStatement (SeqBlock       s   ) = "begin\n" <> fold (genStatement <$> s) <> "end\n"
+genStatement (BlockAssign    a   ) = genAssign " = " a <> ";\n"
+genStatement (NonBlockAssign a   ) = genAssign " <= " a <> ";\n"
+genStatement (StatCA         a   ) = genContAssign a
+genStatement (TaskEnable     task) = genTask task <> ";\n"
+genStatement (SysTaskEnable  task) = "$" <> genTask task <> ";\n"
 
 genTask :: Task -> Text
 genTask (Task name expr)
@@ -245,8 +245,8 @@ instance Source Identifier where
 instance Source Task where
     genSource = genTask
 
-instance Source Stmnt where
-    genSource = genStmnt
+instance Source Statement where
+    genSource = genStatement
 
 instance Source PortType where
     genSource = genPortType
diff --git a/src/VeriFuzz/Icarus.hs b/src/VeriFuzz/Icarus.hs
index b709967..dc2474d 100644
--- a/src/VeriFuzz/Icarus.hs
+++ b/src/VeriFuzz/Icarus.hs
@@ -50,7 +50,7 @@ instance Simulator Icarus where
 defaultIcarus :: Icarus
 defaultIcarus = Icarus "iverilog" "vvp"
 
-addDisplay :: [Stmnt] -> [Stmnt]
+addDisplay :: [Statement] -> [Statement]
 addDisplay s = concat $ transpose
     [ s
     , replicate l $ TimeCtrl 1 Nothing
@@ -58,7 +58,7 @@ addDisplay s = concat $ transpose
     ]
     where l = length s
 
-assignFunc :: [Port] -> ByteString -> Stmnt
+assignFunc :: [Port] -> ByteString -> Statement
 assignFunc inp bs =
     NonBlockAssign . Assign conc Nothing . Number (B.length bs * 8) $ bsToI bs
     where conc = RegConcat (portToExpr <$> inp)