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author | Yann Herklotz <git@ymhg.org> | 2019-04-02 13:05:06 +0100 |
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committer | Yann Herklotz <git@ymhg.org> | 2019-04-02 13:05:06 +0100 |
commit | 5938621be5321e7e2f26735227977c9716a22e12 (patch) | |
tree | a7dc9bd661fdeec549d2ac565a75989050d4f977 /src/VeriFuzz | |
parent | 9791ad6df2867be8f4a7015d23e9ad892bd44354 (diff) | |
download | verismith-5938621be5321e7e2f26735227977c9716a22e12.tar.gz verismith-5938621be5321e7e2f26735227977c9716a22e12.zip |
Fix Circuit types
Diffstat (limited to 'src/VeriFuzz')
-rw-r--r-- | src/VeriFuzz/Circuit.hs | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/src/VeriFuzz/Circuit.hs b/src/VeriFuzz/Circuit.hs index b3f8dcd..af534a2 100644 --- a/src/VeriFuzz/Circuit.hs +++ b/src/VeriFuzz/Circuit.hs @@ -15,12 +15,12 @@ module VeriFuzz.Circuit Gate(..) , Circuit(..) , CNode(..) + , CEdge(..) ) where -import Data.Graph.Inductive (Gr, LNode) +import Data.Graph.Inductive (Gr, LEdge, LNode) import System.Random -import Test.QuickCheck -- | The types for all the gates. data Gate = And @@ -33,12 +33,11 @@ newtype Circuit = Circuit { getCircuit :: Gr Gate () } newtype CNode = CNode { getCNode :: LNode Gate } +newtype CEdge = CEdge { getCEdge :: LEdge () } + instance Random Gate where randomR (a, b) g = case randomR (fromEnum a, fromEnum b) g of (x, g') -> (toEnum x, g') random = randomR (minBound, maxBound) - -instance Arbitrary Gate where - arbitrary = elements [And, Or, Xor] |