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| author | Yann Herklotz <git@yannherklotz.com> | 2019-09-18 19:06:32 +0200 |
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| committer | Yann Herklotz <git@yannherklotz.com> | 2019-09-18 19:06:32 +0200 |
| commit | 8d96fd2a541a2602544ced741552ebd17714c67d (patch) | |
| tree | 2f53addec05793cf5b3e0274a3e8e9e5f76a7abe /src/VeriSmith/Circuit.hs | |
| parent | d14196cce14d1b4a4a9fba768b9f5238c8626624 (diff) | |
| download | verismith-8d96fd2a541a2602544ced741552ebd17714c67d.tar.gz verismith-8d96fd2a541a2602544ced741552ebd17714c67d.zip | |
Rename main modules
Diffstat (limited to 'src/VeriSmith/Circuit.hs')
| -rw-r--r-- | src/VeriSmith/Circuit.hs | 45 |
1 files changed, 0 insertions, 45 deletions
diff --git a/src/VeriSmith/Circuit.hs b/src/VeriSmith/Circuit.hs deleted file mode 100644 index aee0d57..0000000 --- a/src/VeriSmith/Circuit.hs +++ /dev/null @@ -1,45 +0,0 @@ -{-| -Module : VeriSmith.Circuit -Description : Definition of the circuit graph. -Copyright : (c) 2018-2019, Yann Herklotz -License : BSD-3 -Maintainer : yann [at] yannherklotz [dot] com -Stability : experimental -Portability : POSIX - -Definition of the circuit graph. --} - -module VeriSmith.Circuit - ( -- * Circuit - Gate(..) - , Circuit(..) - , CNode(..) - , CEdge(..) - , fromGraph - , generateAST - , rDups - , rDupsCirc - , randomDAG - , genRandomDAG - ) -where - -import Control.Lens -import Hedgehog (Gen) -import qualified Hedgehog.Gen as Hog -import VeriSmith.Circuit.Base -import VeriSmith.Circuit.Gen -import VeriSmith.Circuit.Random -import VeriSmith.Verilog.AST -import VeriSmith.Verilog.Mutate - -fromGraph :: Gen ModDecl -fromGraph = do - gr <- rDupsCirc <$> Hog.resize 100 randomDAG - return - $ initMod - . head - $ nestUpTo 5 (generateAST gr) - ^.. _Wrapped - . traverse |