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author | Yann Herklotz <git@yannherklotz.com> | 2019-10-29 12:06:05 +0000 |
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committer | Yann Herklotz <git@yannherklotz.com> | 2019-10-29 12:06:05 +0000 |
commit | 4ee6646b8a78d4c20fe0b89d95f23d382e1c47fc (patch) | |
tree | 9b02e1b92f8abf0baf3dc108ab7f4fb8f33e753a /src/Verismith/Circuit.hs | |
parent | 1aaff80235237507572e0fb4be86f34cb1829b68 (diff) | |
parent | 01c2ab3f6a58d416528efce3057e2cf2f1604489 (diff) | |
download | verismith-4ee6646b8a78d4c20fe0b89d95f23d382e1c47fc.tar.gz verismith-4ee6646b8a78d4c20fe0b89d95f23d382e1c47fc.zip |
Merge branch 'master' into HEADfeature/nondeterminism
Diffstat (limited to 'src/Verismith/Circuit.hs')
-rw-r--r-- | src/Verismith/Circuit.hs | 45 |
1 files changed, 45 insertions, 0 deletions
diff --git a/src/Verismith/Circuit.hs b/src/Verismith/Circuit.hs new file mode 100644 index 0000000..81eec12 --- /dev/null +++ b/src/Verismith/Circuit.hs @@ -0,0 +1,45 @@ +{-| +Module : Verismith.Circuit +Description : Definition of the circuit graph. +Copyright : (c) 2018-2019, Yann Herklotz +License : BSD-3 +Maintainer : yann [at] yannherklotz [dot] com +Stability : experimental +Portability : POSIX + +Definition of the circuit graph. +-} + +module Verismith.Circuit + ( -- * Circuit + Gate(..) + , Circuit(..) + , CNode(..) + , CEdge(..) + , fromGraph + , generateAST + , rDups + , rDupsCirc + , randomDAG + , genRandomDAG + ) +where + +import Control.Lens +import Hedgehog (Gen) +import qualified Hedgehog.Gen as Hog +import Verismith.Circuit.Base +import Verismith.Circuit.Gen +import Verismith.Circuit.Random +import Verismith.Verilog.AST +import Verismith.Verilog.Mutate + +fromGraph :: Gen ModDecl +fromGraph = do + gr <- rDupsCirc <$> Hog.resize 100 randomDAG + return + $ initMod + . head + $ nestUpTo 5 (generateAST gr) + ^.. _Wrapped + . traverse |