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author | Yann Herklotz <git@yannherklotz.com> | 2019-10-29 12:06:05 +0000 |
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committer | Yann Herklotz <git@yannherklotz.com> | 2019-10-29 12:06:05 +0000 |
commit | 4ee6646b8a78d4c20fe0b89d95f23d382e1c47fc (patch) | |
tree | 9b02e1b92f8abf0baf3dc108ab7f4fb8f33e753a /src/Verismith/Circuit/Base.hs | |
parent | 1aaff80235237507572e0fb4be86f34cb1829b68 (diff) | |
parent | 01c2ab3f6a58d416528efce3057e2cf2f1604489 (diff) | |
download | verismith-4ee6646b8a78d4c20fe0b89d95f23d382e1c47fc.tar.gz verismith-4ee6646b8a78d4c20fe0b89d95f23d382e1c47fc.zip |
Merge branch 'master' into HEADfeature/nondeterminism
Diffstat (limited to 'src/Verismith/Circuit/Base.hs')
-rw-r--r-- | src/Verismith/Circuit/Base.hs | 44 |
1 files changed, 44 insertions, 0 deletions
diff --git a/src/Verismith/Circuit/Base.hs b/src/Verismith/Circuit/Base.hs new file mode 100644 index 0000000..9a5ab34 --- /dev/null +++ b/src/Verismith/Circuit/Base.hs @@ -0,0 +1,44 @@ +{-| +Module : Verismith.Circuit.Base +Description : Base types for the circuit module. +Copyright : (c) 2019, Yann Herklotz Grave +License : GPL-3 +Maintainer : yann [at] yannherklotz [dot] com +Stability : experimental +Portability : POSIX + +Base types for the circuit module. +-} + +module Verismith.Circuit.Base + ( Gate(..) + , Circuit(..) + , CNode(..) + , CEdge(..) + ) +where + +import Data.Graph.Inductive (Gr, LEdge, LNode) +import System.Random + +-- | The types for all the gates. +data Gate = And + | Or + | Xor + deriving (Show, Eq, Enum, Bounded, Ord) + +-- | Newtype for the Circuit which implements a Graph from fgl. +newtype Circuit = Circuit { getCircuit :: Gr Gate () } + +-- | Newtype for a node in the circuit, which is an 'LNode Gate'. +newtype CNode = CNode { getCNode :: LNode Gate } + +-- | Newtype for a named edge which is empty, as it does not need a label. +newtype CEdge = CEdge { getCEdge :: LEdge () } + +instance Random Gate where + randomR (a, b) g = + case randomR (fromEnum a, fromEnum b) g of + (x, g') -> (toEnum x, g') + + random = randomR (minBound, maxBound) |