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author | Yann Herklotz <git@yannherklotz.com> | 2020-04-09 16:35:03 +0100 |
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committer | Yann Herklotz <git@yannherklotz.com> | 2020-04-09 16:35:03 +0100 |
commit | 659e25c9d5b8a31ab3b8412b658c5e7b11f9408e (patch) | |
tree | 80063bda340f6dc72e4d0ad911a229b443c2819b /src/Verismith/Verilog | |
parent | d86cb8fd763e687cf2cd7ad40094d15ebba6bf87 (diff) | |
download | verismith-659e25c9d5b8a31ab3b8412b658c5e7b11f9408e.tar.gz verismith-659e25c9d5b8a31ab3b8412b658c5e7b11f9408e.zip |
Add option to drop reg and wire from output
Diffstat (limited to 'src/Verismith/Verilog')
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