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authorYann Herklotz <git@ymhg.org>2019-05-14 18:46:18 +0100
committerYann Herklotz <git@ymhg.org>2019-05-14 18:46:18 +0100
commit0ac7a07f5320dfe3372821c41269f1da1b3ba6c8 (patch)
tree8545a8b3f14b18d374cf25d0546284147f6c76b1 /src
parent777bd910952496b8bff5fd2795badc32d5c0561b (diff)
downloadverismith-0ac7a07f5320dfe3372821c41269f1da1b3ba6c8.tar.gz
verismith-0ac7a07f5320dfe3372821c41269f1da1b3ba6c8.zip
Optimisations in the generation
Diffstat (limited to 'src')
-rw-r--r--src/VeriFuzz/Verilog/Gen.hs10
1 files changed, 4 insertions, 6 deletions
diff --git a/src/VeriFuzz/Verilog/Gen.hs b/src/VeriFuzz/Verilog/Gen.hs
index 0cff33a..96a90f9 100644
--- a/src/VeriFuzz/Verilog/Gen.hs
+++ b/src/VeriFuzz/Verilog/Gen.hs
@@ -347,20 +347,18 @@ statement = do
where onDepth c n = if c ^. stmntDepth > 0 then n else 0
alwaysSeq :: StateGen ModItem
-alwaysSeq = do
- stat <- seqBlock
- return $ Always (EventCtrl (EPosEdge "clk") (Just stat))
+alwaysSeq = Always . EventCtrl (EPosEdge "clk") . Just <$> seqBlock
instantiate :: ModDecl -> StateGen ModItem
instantiate (ModDecl i outP inP _ _) = do
context <- get
- outs <-
- fmap (Id . view portName) <$> (replicateM (length outP) $ nextPort Wire)
+ outs <- fmap (Id . view portName)
+ <$> replicateM (length outP) (nextPort Wire)
ins <-
(Id "clk" :)
. fmap (Id . view portName)
. take (length inP - 1)
- <$> (Hog.shuffle $ context ^. variables)
+ <$> Hog.shuffle (context ^. variables)
ident <- makeIdentifier "modinst"
Hog.choice
[ return . ModInst i ident $ ModConn <$> outs <> ins