More restructuring

15 files changed, 26 insertions, 130 deletions

diff --git a/src/VeriFuzz/Verilog/AST.hs b/src/VeriFuzz/AST.hs
index 0f24c49..0f24c49 100644
--- a/src/VeriFuzz/Verilog/AST.hs
+++ b/src/VeriFuzz/AST.hs
diff --git a/src/VeriFuzz/Circuit/ASTGen.hs b/src/VeriFuzz/ASTGen.hs
index 41f905d..41f905d 100644
--- a/src/VeriFuzz/Circuit/ASTGen.hs
+++ b/src/VeriFuzz/ASTGen.hs
diff --git a/src/VeriFuzz/Circuit/CodeGen.hs b/src/VeriFuzz/Circuit/CodeGen.hs
deleted file mode 100644
index 91da48c..0000000
--- a/src/VeriFuzz/Circuit/CodeGen.hs
+++ /dev/null
@@ -1,62 +0,0 @@
-{-|
-Module      : VeriFuzz.Circuit.Random
-Description : Code generation directly from DAG.
-Copyright   : (c) 2018-2019, Yann Herklotz Grave
-License     : BSD-3
-Maintainer  : ymherklotz [at] gmail [dot] com
-Stability   : experimental
-Portability : POSIX
-
-Define the code generation directly from the random DAG.
--}
-
-module VeriFuzz.Circuit.CodeGen
-  ( generate
-  )
-where
-
-import           Data.Foldable            (fold)
-import           Data.Graph.Inductive     (Graph, LNode, Node, labNodes, pre)
-import           Data.Maybe               (fromMaybe)
-import           Data.Text                (Text)
-import qualified Data.Text                as T
-import           VeriFuzz.Circuit
-import           VeriFuzz.Internal.Gen
-import           VeriFuzz.Internal.Shared
-
-toOperator :: Gate -> Text
-toOperator And = " & "
-toOperator Or  = " | "
-toOperator Xor = " ^ "
-
-statList :: Gate -> [Node] -> Maybe Text
-statList g n = toStr <$> safe tail n where toStr = fold . fmap ((<> toOperator g) . fromNode)
-
-lastEl :: [Node] -> Maybe Text
-lastEl n = fromNode <$> safe head n
-
-toStmnt :: (Graph gr) => gr Gate e -> LNode Gate -> Text
-toStmnt graph (n, g) =
-  fromMaybe T.empty
-    $  Just "  assign "
-    <> Just (fromNode n)
-    <> Just " = "
-    <> statList g nodeL
-    <> lastEl nodeL
-    <> Just ";\n"
-  where nodeL = pre graph n
-
-generate :: (Graph gr) => gr Gate e -> Text
-generate graph =
-  "module generated_module(\n"
-    <> fold (imap "  input wire " ",\n" inp)
-    <> T.intercalate ",\n" (imap "  output wire " "" out)
-    <> ");\n"
-    <> fold (toStmnt graph <$> labNodes graph)
-    <> "endmodule\n\nmodule main;\n  initial\n    begin\n      "
-    <> "$display(\"Hello, world\");\n      $finish;\n    "
-    <> "end\nendmodule"
- where
-  inp = inputs graph
-  out = outputs graph
-  imap b e = fmap ((\s -> b <> s <> e) . fromNode)
diff --git a/src/VeriFuzz/Verilog/CodeGen.hs b/src/VeriFuzz/CodeGen.hs
index 3253f86..3253f86 100644
--- a/src/VeriFuzz/Verilog/CodeGen.hs
+++ b/src/VeriFuzz/CodeGen.hs
diff --git a/src/VeriFuzz/Env.hs b/src/VeriFuzz/Env.hs
new file mode 100644
index 0000000..85c761e
--- /dev/null
+++ b/src/VeriFuzz/Env.hs
@@ -0,0 +1,26 @@
+{-|
+Module      : VeriFuzz.Env
+Description : Environment to run the simulator and synthesisers in a matrix.
+Copyright   : (c) 2019, Yann Herklotz Grave
+License     : GPL-3
+Maintainer  : ymherklotz [at] gmail [dot] com
+Stability   : experimental
+Portability : POSIX
+
+Environment to run the simulator and synthesisers in a matrix.
+-}
+
+module VeriFuzz.Env where
+
+-- | Environment used to run the main
+data SimMatrix = SimMatrix { yosys  :: Yosys
+                           , xst    :: Maybe Xst
+                           , icarus :: Maybe Icarus
+                           }
+
+type SimEnv = ReaderT SimMatrix IO
+
+runAll :: SimEnv ()
+runAll = do
+  val <- asks xst
+  shelly $ run_ "echo" ["Hello World"]
diff --git a/src/VeriFuzz/Simulator/General.hs b/src/VeriFuzz/General.hs
index dbd1da0..dbd1da0 100644
--- a/src/VeriFuzz/Simulator/General.hs
+++ b/src/VeriFuzz/General.hs
diff --git a/src/VeriFuzz/Verilog/Helpers.hs b/src/VeriFuzz/Helpers.hs
index 99e5f38..99e5f38 100644
--- a/src/VeriFuzz/Verilog/Helpers.hs
+++ b/src/VeriFuzz/Helpers.hs
diff --git a/src/VeriFuzz/Simulator/Icarus.hs b/src/VeriFuzz/Icarus.hs
index 527322a..527322a 100644
--- a/src/VeriFuzz/Simulator/Icarus.hs
+++ b/src/VeriFuzz/Icarus.hs
diff --git a/src/VeriFuzz/Verilog/Mutate.hs b/src/VeriFuzz/Mutate.hs
index 3e03a02..3e03a02 100644
--- a/src/VeriFuzz/Verilog/Mutate.hs
+++ b/src/VeriFuzz/Mutate.hs
diff --git a/src/VeriFuzz/Circuit/Random.hs b/src/VeriFuzz/Random.hs
index 7989b49..7989b49 100644
--- a/src/VeriFuzz/Circuit/Random.hs
+++ b/src/VeriFuzz/Random.hs
diff --git a/src/VeriFuzz/Circuit/RandomAlt.hs b/src/VeriFuzz/RandomAlt.hs
index 93a50e9..93a50e9 100644
--- a/src/VeriFuzz/Circuit/RandomAlt.hs
+++ b/src/VeriFuzz/RandomAlt.hs
diff --git a/src/VeriFuzz/Simulator.hs b/src/VeriFuzz/Simulator.hs
deleted file mode 100644
index a84cd5f..0000000
--- a/src/VeriFuzz/Simulator.hs
+++ /dev/null
@@ -1,41 +0,0 @@
-{-|
-Module      : VeriFuzz.Simulator
-Description : Simulator module.
-Copyright   : (c) 2018-2019, Yann Herklotz Grave
-License     : BSD-3
-Maintainer  : ymherklotz [at] gmail [dot] com
-Stability   : experimental
-Portability : POSIX
-
-Simulator module.
--}
-
-module VeriFuzz.Simulator
-  ( SimMatrix
-  , module VeriFuzz.Simulator.General
-  , module VeriFuzz.Simulator.Yosys
-  , module VeriFuzz.Simulator.Xst
-  , module VeriFuzz.Simulator.Icarus
-  )
-where
-
-import           Control.Monad.Trans.Reader
-import           Prelude                    hiding (FilePath)
-import           Shelly
-import           VeriFuzz.Simulator.General
-import           VeriFuzz.Simulator.Icarus
-import           VeriFuzz.Simulator.Xst
-import           VeriFuzz.Simulator.Yosys
-
--- | Environment used to run the main
-data SimMatrix = SimMatrix { yosys  :: Yosys
-                           , xst    :: Maybe Xst
-                           , icarus :: Maybe Icarus
-                           }
-
-type SimEnv = ReaderT SimMatrix IO
-
-runAll :: SimEnv ()
-runAll = do
-  val <- asks xst
-  shelly $ run_ "echo" ["Hello World"]
diff --git a/src/VeriFuzz/Verilog.hs b/src/VeriFuzz/Verilog.hs
deleted file mode 100644
index 6b6a13f..0000000
--- a/src/VeriFuzz/Verilog.hs
+++ /dev/null
@@ -1,27 +0,0 @@
-{-|
-Module      : VeriFuzz.Verilog
-Description : The main verilog module with the syntax and code generation.
-Copyright   : (c) 2018-2019, Yann Herklotz Grave
-License     : BSD-3
-Maintainer  : ymherklotz [at] gmail [dot] com
-Stability   : experimental
-Portability : POSIX
-
-The main verilog module with the syntax and code generation.
--}
-
-module VeriFuzz.Verilog
-  ( -- * AST
-    module VeriFuzz.Verilog.AST
-    -- * Code Generation
-  , module VeriFuzz.Verilog.CodeGen
-    -- * Verilog mutations
-  , module VeriFuzz.Verilog.Mutate
-  , module VeriFuzz.Verilog.Helpers
-  )
-where
-
-import           VeriFuzz.Verilog.AST
-import           VeriFuzz.Verilog.CodeGen
-import           VeriFuzz.Verilog.Helpers
-import           VeriFuzz.Verilog.Mutate
diff --git a/src/VeriFuzz/Simulator/Xst.hs b/src/VeriFuzz/Xst.hs
index 52272c3..52272c3 100644
--- a/src/VeriFuzz/Simulator/Xst.hs
+++ b/src/VeriFuzz/Xst.hs
diff --git a/src/VeriFuzz/Simulator/Yosys.hs b/src/VeriFuzz/Yosys.hs
index e18de5a..e18de5a 100644
--- a/src/VeriFuzz/Simulator/Yosys.hs
+++ b/src/VeriFuzz/Yosys.hs