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authorYann Herklotz <git@yannherklotz.com>2019-05-25 23:26:27 +0100
committerYann Herklotz <git@yannherklotz.com>2019-05-25 23:26:27 +0100
commit11bd73faa516cde0af74e5359c36c8f1fa4e816a (patch)
tree55761b9b97d547686a565943a490eb58d93d3f18 /src
parent3ad518489f1528941d4d059e594ad9ac1d22fd0d (diff)
downloadverismith-11bd73faa516cde0af74e5359c36c8f1fa4e816a.tar.gz
verismith-11bd73faa516cde0af74e5359c36c8f1fa4e816a.zip
Fix reduction for statements
Diffstat (limited to 'src')
-rw-r--r--src/VeriFuzz.hs7
-rw-r--r--src/VeriFuzz/Reduce.hs26
-rw-r--r--src/VeriFuzz/Verilog.hs2
3 files changed, 20 insertions, 15 deletions
diff --git a/src/VeriFuzz.hs b/src/VeriFuzz.hs
index 6d4f839..4b9878d 100644
--- a/src/VeriFuzz.hs
+++ b/src/VeriFuzz.hs
@@ -400,9 +400,10 @@ handleOpts (Reduce f t _ ls' True) = do
runSynth b src
runEquiv a b src
case res of
- Pass _ -> putStrLn "Equivalence check passed"
- Fail EquivFail -> error "Equivalence check failed"
- Fail _ -> error "Equivalence check errored out"
+ Pass _ -> putStrLn "Equivalence check passed"
+ Fail EquivFail -> putStrLn "Equivalence check failed"
+ Fail TimeoutError -> putStrLn "Equivalence check timed out"
+ Fail _ -> putStrLn "Equivalence check error"
return ()
as -> do
putStrLn "Synthesis check"
diff --git a/src/VeriFuzz/Reduce.hs b/src/VeriFuzz/Reduce.hs
index b025a42..2f44c07 100644
--- a/src/VeriFuzz/Reduce.hs
+++ b/src/VeriFuzz/Reduce.hs
@@ -35,27 +35,28 @@ module VeriFuzz.Reduce
)
where
-import Control.Lens hiding ((<.>))
-import Control.Monad (void)
-import Control.Monad.IO.Class (MonadIO, liftIO)
-import Data.Foldable (foldrM)
-import Data.List (nub)
-import Data.List.NonEmpty (NonEmpty (..))
-import qualified Data.List.NonEmpty as NonEmpty
-import Data.Maybe (mapMaybe)
-import Data.Text (Text)
-import Shelly ((<.>))
+import Control.Lens hiding ((<.>))
+import Control.Monad (void)
+import Control.Monad.IO.Class (MonadIO, liftIO)
+import Data.Foldable (foldrM)
+import Data.List (nub)
+import Data.List.NonEmpty (NonEmpty (..))
+import qualified Data.List.NonEmpty as NonEmpty
+import Data.Maybe (mapMaybe)
+import Data.Text (Text)
+import Shelly ((<.>))
import qualified Shelly
-import Shelly.Lifted (MonadSh, liftSh)
+import Shelly.Lifted (MonadSh, liftSh)
import VeriFuzz.Internal
import VeriFuzz.Result
import VeriFuzz.Sim
import VeriFuzz.Sim.Internal
+import VeriFuzz.Verilog
import VeriFuzz.Verilog.AST
-import VeriFuzz.Verilog.CodeGen
import VeriFuzz.Verilog.Mutate
import VeriFuzz.Verilog.Parser
+
-- $strategy
-- The reduction strategy has multiple different steps. 'reduce' will run these
-- strategies one after another, starting at the most coarse grained one. The
@@ -334,6 +335,7 @@ matchesModName :: Identifier -> ModDecl -> Bool
matchesModName top (ModDecl i _ _ _ _) = top == i
halveStatement :: Replace Statement
+halveStatement (SeqBlock [s]) = halveStatement s
halveStatement (SeqBlock s) = SeqBlock <$> halve s
halveStatement (CondStmnt _ (Just s1) (Just s2)) = Dual s1 s2
halveStatement (CondStmnt _ (Just s1) Nothing) = Single s1
diff --git a/src/VeriFuzz/Verilog.hs b/src/VeriFuzz/Verilog.hs
index 3e8d2c7..628b00a 100644
--- a/src/VeriFuzz/Verilog.hs
+++ b/src/VeriFuzz/Verilog.hs
@@ -10,6 +10,8 @@ Portability : POSIX
Verilog implementation with random generation and mutations.
-}
+{-# LANGUAGE QuasiQuotes #-}
+
module VeriFuzz.Verilog
( SourceInfo(..)
, Verilog(..)