Add constant expression to expression conversion and vice versa

2 files changed, 23 insertions, 0 deletions

diff --git a/src/VeriFuzz/Verilog.hs b/src/VeriFuzz/Verilog.hs
index 4f9fd52..701a7d6 100644
--- a/src/VeriFuzz/Verilog.hs
+++ b/src/VeriFuzz/Verilog.hs
@@ -53,6 +53,8 @@ module VeriFuzz.Verilog
     -- * Expression
     , Expr(..)
     , ConstExpr(..)
+    , constToExpr
+    , exprToConst
     , constNum
     -- * Assignment
     , Assign(..)
diff --git a/src/VeriFuzz/Verilog/AST.hs b/src/VeriFuzz/Verilog/AST.hs
index c4d889b..30634c0 100644
--- a/src/VeriFuzz/Verilog/AST.hs
+++ b/src/VeriFuzz/Verilog/AST.hs
@@ -59,6 +59,8 @@ module VeriFuzz.Verilog.AST
     , Expr(..)
     , ConstExpr(..)
     , ConstExprF(..)
+    , constToExpr
+    , exprToConst
     , Range(..)
     , constNum
     , constParamId
@@ -265,6 +267,25 @@ data ConstExpr = ConstNum { _constNum :: {-# UNPACK #-} !BitVec }
                | ConstStr { _constStr :: {-# UNPACK #-} !Text }
                deriving (Eq, Show, Ord, Data)
 
+constToExpr :: ConstExpr -> Expr
+constToExpr (ConstNum a)    = Number a
+constToExpr (ParamId a)     = Id a
+constToExpr (ConstConcat a) = Concat $ fmap constToExpr a
+constToExpr (ConstUnOp a b) = UnOp a $ constToExpr b
+constToExpr (ConstBinOp a b c) = BinOp (constToExpr a) b $ constToExpr c
+constToExpr (ConstCond a b c) = Cond (constToExpr a) (constToExpr b) $ constToExpr c
+constToExpr (ConstStr a) = Str a
+
+exprToConst :: Expr -> ConstExpr
+exprToConst (Number a)    = ConstNum a
+exprToConst (Id a)     = ParamId a
+exprToConst (Concat a) = ConstConcat $ fmap exprToConst a
+exprToConst (UnOp a b) = ConstUnOp a $ exprToConst b
+exprToConst (BinOp a b c) = ConstBinOp (exprToConst a) b $ exprToConst c
+exprToConst (Cond a b c) = ConstCond (exprToConst a) (exprToConst b) $ exprToConst c
+exprToConst (Str a) = ConstStr a
+exprToConst _ = error "Not a constant expression"
+
 instance Num ConstExpr where
   a + b = ConstBinOp a BinPlus b
   a - b = ConstBinOp a BinMinus b