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| author | Yann Herklotz <git@ymhg.org> | 2019-05-15 00:54:22 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@ymhg.org> | 2019-05-15 00:54:22 +0100 |
| commit | 37104090c7f133fae523e840079f8a8bd7ab213b (patch) | |
| tree | 95705e0f03bf22675dc86f15fb6e798588737ab5 /src | |
| parent | 9478e8bb30a21eaf08b1f4b6bbf73bf466ee77f7 (diff) | |
| download | verismith-37104090c7f133fae523e840079f8a8bd7ab213b.tar.gz verismith-37104090c7f133fae523e840079f8a8bd7ab213b.zip | |
Remove modConn lens and replace by modExpr
Diffstat (limited to 'src')
| -rw-r--r-- | src/VeriFuzz/Verilog.hs | 1 | ||||
| -rw-r--r-- | src/VeriFuzz/Verilog/AST.hs | 6 |
2 files changed, 3 insertions, 4 deletions
diff --git a/src/VeriFuzz/Verilog.hs b/src/VeriFuzz/Verilog.hs index 399159f..3e8d2c7 100644 --- a/src/VeriFuzz/Verilog.hs +++ b/src/VeriFuzz/Verilog.hs @@ -93,7 +93,6 @@ module VeriFuzz.Verilog , declDir , declPort , ModConn(..) - , modConn , modConnName , modExpr -- * Useful Lenses and Traversals diff --git a/src/VeriFuzz/Verilog/AST.hs b/src/VeriFuzz/Verilog/AST.hs index c8d85e6..306366c 100644 --- a/src/VeriFuzz/Verilog/AST.hs +++ b/src/VeriFuzz/Verilog/AST.hs @@ -129,7 +129,6 @@ module VeriFuzz.Verilog.AST , declPort , declVal , ModConn(..) - , modConn , modConnName , modExpr -- * Useful Lenses and Traversals @@ -388,7 +387,7 @@ data Port = Port { _portType :: !PortType -- @ -- mod a(.y(y1), .x1(x11), .x2(x22)); -- @ -data ModConn = ModConn { _modConn :: !Expr } +data ModConn = ModConn { _modExpr :: !Expr } | ModConnNamed { _modConnName :: {-# UNPACK #-} !Identifier , _modExpr :: !Expr } @@ -536,7 +535,8 @@ aModule t = lens get_ set_ SourceInfo top (main & getModule %~ update (getIdentifier t) v) update top v m@(ModDecl (Identifier i) _ _ _ _) | i == top = v | otherwise = m - get_ (SourceInfo _ main) = head . filter (f $ getIdentifier t) $ main ^.. getModule + get_ (SourceInfo _ main) = + head . filter (f $ getIdentifier t) $ main ^.. getModule f top (ModDecl (Identifier i) _ _ _ _) = i == top |