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| author | Yann Herklotz <git@ymhg.org> | 2019-05-10 17:40:57 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@ymhg.org> | 2019-05-10 17:40:57 +0100 |
| commit | 8241ebad9374187b20ee0fdd43029a2a5ddfbb4e (patch) | |
| tree | 5b1ef5dd36b07c1e4a29b9049f2bcbb15094a118 /src | |
| parent | 06c61e705d952679a6200e7d18d2463723fe5878 (diff) | |
| download | verismith-8241ebad9374187b20ee0fdd43029a2a5ddfbb4e.tar.gz verismith-8241ebad9374187b20ee0fdd43029a2a5ddfbb4e.zip | |
Fix but remove the doctests for now
They were not working well with the current printing method. I have to find a
way to remove the spaces from the output.
Diffstat (limited to 'src')
| -rw-r--r-- | src/VeriFuzz/Reduce.hs | 50 |
1 files changed, 25 insertions, 25 deletions
diff --git a/src/VeriFuzz/Reduce.hs b/src/VeriFuzz/Reduce.hs index 48a3c78..df92d99 100644 --- a/src/VeriFuzz/Reduce.hs +++ b/src/VeriFuzz/Reduce.hs @@ -188,14 +188,14 @@ halveExpr = combine contexpr $ traverse halveModExpr -- -- >>> GenVerilog srcInfo -- module top(y, x); --- output wire [(3'h4):(1'h0)] y; --- input wire [(3'h4):(1'h0)] x; --- m m(y, x); +-- output wire [(3'h4):(1'h0)] y; +-- input wire [(3'h4):(1'h0)] x; +-- m m(y, x); -- endmodule -- <BLANKLINE> -- module m(y, x); --- output wire [(3'h4):(1'h0)] y; --- input wire [(3'h4):(1'h0)] x; +-- output wire [(3'h4):(1'h0)] y; +-- input wire [(3'h4):(1'h0)] x; -- endmodule -- <BLANKLINE> -- <BLANKLINE> @@ -203,28 +203,28 @@ halveExpr = combine contexpr $ traverse halveModExpr -- >>> GenVerilog <$> halveModules srcInfo -- --- Only try: -- module top(y, x); --- output wire [(3'h4):(1'h0)] y; --- input wire [(3'h4):(1'h0)] x; +-- output wire [(3'h4):(1'h0)] y; +-- input wire [(3'h4):(1'h0)] x; -- endmodule -- <BLANKLINE> -- <BLANKLINE> -- -- >>> GenVerilog srcInfo2 -- module top(y, x); --- output wire [(3'h4):(1'h0)] y; --- input wire [(3'h4):(1'h0)] x; --- m m(y, x); --- m2 m2(y, x); +-- output wire [(3'h4):(1'h0)] y; +-- input wire [(3'h4):(1'h0)] x; +-- m m(y, x); +-- m2 m2(y, x); -- endmodule -- <BLANKLINE> -- module m(y, x); --- output wire [(3'h4):(1'h0)] y; --- input wire [(3'h4):(1'h0)] x; +-- output wire [(3'h4):(1'h0)] y; +-- input wire [(3'h4):(1'h0)] x; -- endmodule -- <BLANKLINE> -- module m2(y, x); --- output wire [(3'h4):(1'h0)] y; --- input wire [(3'h4):(1'h0)] x; +-- output wire [(3'h4):(1'h0)] y; +-- input wire [(3'h4):(1'h0)] x; -- endmodule -- <BLANKLINE> -- <BLANKLINE> @@ -232,27 +232,27 @@ halveExpr = combine contexpr $ traverse halveModExpr -- >>> GenVerilog <$> halveModules srcInfo2 -- --- Try: -- module top(y, x); --- output wire [(3'h4):(1'h0)] y; --- input wire [(3'h4):(1'h0)] x; --- m m(y, x); +-- output wire [(3'h4):(1'h0)] y; +-- input wire [(3'h4):(1'h0)] x; +-- m m(y, x); -- endmodule -- <BLANKLINE> -- module m(y, x); --- output wire [(3'h4):(1'h0)] y; --- input wire [(3'h4):(1'h0)] x; +-- output wire [(3'h4):(1'h0)] y; +-- input wire [(3'h4):(1'h0)] x; -- endmodule -- <BLANKLINE> -- <BLANKLINE> -- --- Then: -- module top(y, x); --- output wire [(3'h4):(1'h0)] y; --- input wire [(3'h4):(1'h0)] x; --- m2 m2(y, x); +-- output wire [(3'h4):(1'h0)] y; +-- input wire [(3'h4):(1'h0)] x; +-- m2 m2(y, x); -- endmodule -- <BLANKLINE> -- module m2(y, x); --- output wire [(3'h4):(1'h0)] y; --- input wire [(3'h4):(1'h0)] x; +-- output wire [(3'h4):(1'h0)] y; +-- input wire [(3'h4):(1'h0)] x; -- endmodule -- <BLANKLINE> -- <BLANKLINE> |