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| author | Yann Herklotz <git@yannherklotz.com> | 2019-05-26 16:25:40 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2019-05-26 16:26:02 +0100 |
| commit | 87b0f99853072ad1b17b380726b3807f6f4f91d4 (patch) | |
| tree | 3ee3d95eb9603d4542173d80ed0c45c6adc492f3 /src | |
| parent | 11bd73faa516cde0af74e5359c36c8f1fa4e816a (diff) | |
| download | verismith-87b0f99853072ad1b17b380726b3807f6f4f91d4.tar.gz verismith-87b0f99853072ad1b17b380726b3807f6f4f91d4.zip | |
Add changes to work with older Vivado
Diffstat (limited to 'src')
| -rw-r--r-- | src/VeriFuzz/Sim/Vivado.hs | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/VeriFuzz/Sim/Vivado.hs b/src/VeriFuzz/Sim/Vivado.hs index 9f48188..90eed2d 100644 --- a/src/VeriFuzz/Sim/Vivado.hs +++ b/src/VeriFuzz/Sim/Vivado.hs @@ -56,7 +56,7 @@ runSynthVivado sim (SourceInfo top src) = do writefile vivadoTcl . vivadoSynthConfig top . toTextIgnore $ synthOutput sim writefile "rtl.v" $ genSource src - run_ "sed" ["s/^module/(* use_dsp=\"no\" *) module/;", "-i", "rtl.v"] + run_ "sed" ["s/^module/(* use_dsp48=\"no\" *) (* use_dsp=\"no\" *) module/;", "-i", "rtl.v"] let exec_ n = execute_ SynthFail dir |