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| author | Yann Herklotz <ymherklotz@gmail.com> | 2018-12-01 16:47:58 +0000 |
|---|---|---|
| committer | Yann Herklotz <ymherklotz@gmail.com> | 2018-12-01 16:47:58 +0000 |
| commit | 88d11885a84d09f201db639a98ecf513b519fa0a (patch) | |
| tree | c969abab087850eb7ebcc8647772be13864cff72 /src | |
| parent | be971a09231643850874f30abb7a52af3fe50dce (diff) | |
| download | verismith-88d11885a84d09f201db639a98ecf513b519fa0a.tar.gz verismith-88d11885a84d09f201db639a98ecf513b519fa0a.zip | |
Add modport helper function
Diffstat (limited to 'src')
| -rw-r--r-- | src/Test/VeriFuzz/VerilogAST.hs | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/Test/VeriFuzz/VerilogAST.hs b/src/Test/VeriFuzz/VerilogAST.hs index 109f024..5fdb900 100644 --- a/src/Test/VeriFuzz/VerilogAST.hs +++ b/src/Test/VeriFuzz/VerilogAST.hs @@ -90,3 +90,6 @@ emptyMod = ModuleDecl (Identifier "") [] [] setModName :: Text -> ModuleDecl -> ModuleDecl setModName str = moduleId .~ Identifier str + +addModPort :: Port -> ModuleDecl -> ModuleDecl +addModPort port = modPorts %~ ((:) port) |