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| author | Yann Herklotz <git@ymhg.org> | 2019-05-11 21:52:34 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@ymhg.org> | 2019-05-11 21:52:34 +0100 |
| commit | ed0bdb618c3bbdfda22eae60bfd0dae3a17040e0 (patch) | |
| tree | 256c0a9cf8e9fc88b110c6858a74bbd67abbe3b6 /src | |
| parent | 4486d06ec7e4a5487dc17b6c63ac9a7812a498e0 (diff) | |
| download | verismith-ed0bdb618c3bbdfda22eae60bfd0dae3a17040e0.tar.gz verismith-ed0bdb618c3bbdfda22eae60bfd0dae3a17040e0.zip | |
Add Plate instance to Statement
Diffstat (limited to 'src')
| -rw-r--r-- | src/VeriFuzz/Verilog/AST.hs | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/VeriFuzz/Verilog/AST.hs b/src/VeriFuzz/Verilog/AST.hs index 30634c0..8adf58e 100644 --- a/src/VeriFuzz/Verilog/AST.hs +++ b/src/VeriFuzz/Verilog/AST.hs @@ -119,6 +119,8 @@ module VeriFuzz.Verilog.AST , modInstId , modInstName , modInstConns + , _Initial + , _Always , paramDecl , localParamDecl , traverseModItem @@ -420,6 +422,9 @@ data Statement = TimeCtrl { _statDelay :: {-# UNPACK #-} !Delay } -- ^ Loop bounds shall be statically computable for a for loop. deriving (Eq, Show, Ord, Data) +instance Plated Statement where + plate = uniplate + instance Semigroup Statement where (SeqBlock a) <> (SeqBlock b) = SeqBlock $ a <> b (SeqBlock a) <> b = SeqBlock $ a <> [b] @@ -504,6 +509,7 @@ $(makeLenses ''SourceInfo) $(makeWrapped ''Verilog) $(makeWrapped ''Identifier) $(makeWrapped ''Delay) +$(makePrisms ''ModItem) $(makeBaseFunctor ''Event) $(makeBaseFunctor ''Expr) |