Add recursive reduce call

2 files changed, 35 insertions, 6 deletions

diff --git a/src/VeriFuzz/Parser.hs b/src/VeriFuzz/Parser.hs
index 23329bb..596867c 100644
--- a/src/VeriFuzz/Parser.hs
+++ b/src/VeriFuzz/Parser.hs
@@ -225,8 +225,12 @@ parseModDecl = do
 parseDescription :: Parser Description
 parseDescription = Description <$> lexeme parseModDecl
 
+-- | Parses a 'String' into 'VerilogSrc' by skipping any beginning whitespace
+-- and then parsing multiple Verilog source.
 parseVerilogSrc :: Parser VerilogSrc
 parseVerilogSrc = VerilogSrc <$> (whiteSpace *> many parseDescription)
 
+-- | Parse a 'String' containing verilog code. The parser currently only supports
+-- the subset of Verilog that is being generated randomly.
 parseVerilog :: String -> String -> Either ParseError VerilogSrc
 parseVerilog = parse parseVerilogSrc
diff --git a/src/VeriFuzz/Reduce.hs b/src/VeriFuzz/Reduce.hs
index 35eea4b..6f11767 100644
--- a/src/VeriFuzz/Reduce.hs
+++ b/src/VeriFuzz/Reduce.hs
@@ -10,17 +10,42 @@ Portability : POSIX
 Test case reducer implementation.
 -}
 
-module VeriFuzz.Reduce where
+module VeriFuzz.Reduce
+    ( halveAssigns
+    , reduce
+    )
+where
 
 import           Control.Lens
 import           VeriFuzz.AST
 
+-- | Split a list in two halves.
 halve :: [a] -> ([a], [a])
 halve l = splitAt (length l `div` 2) l
 
-removeUninitWires :: [ModItem] -> [ModItem]
-removeUninitWires ms = ms
-    where ids = ms ^.. traverse . modContAssign . contAssignNetLVal
+-- | Split a module declaration in half by trying to remove assign statements.
+halveAssigns :: VerilogSrc -> (VerilogSrc, VerilogSrc)
+halveAssigns vsrc = (vsrc & vmod %~ fst . halve, vsrc & vmod %~ snd . halve)
+    where
+        vmod = getVerilogSrc . traverse . getDescription . modItems
 
-halveModDecl :: ModDecl -> (ModDecl, ModDecl)
-halveModDecl m = (m & modItems %~ fst . halve, m & modItems %~ snd . halve)
+-- | Reduce an input to a minimal representation.
+reduce :: (VerilogSrc -> IO Bool) -- ^ Failed or not.
+       -> VerilogSrc              -- ^ Input verilog source to be reduced.
+       -> IO VerilogSrc           -- ^ Reduced output.
+reduce eval src = do
+    lresult <- eval l
+    rresult <- eval r
+    case (lresult, rresult) of
+        (True, False) ->
+            reduce eval l
+        (False, True) ->
+            reduce eval r
+        (True, True) ->
+            lreduced <- reduce eval l
+            rreduced <- reduce eval r
+            return lreduced
+        _ ->
+            return src
+    where
+        (l, r) = halveAssigns src