[Fix #38] Fix parser to correctly identify input and output ports

1 files changed, 13 insertions, 2 deletions

diff --git a/src/VeriFuzz/Parser.hs b/src/VeriFuzz/Parser.hs
index 596867c..3e5ddb2 100644
--- a/src/VeriFuzz/Parser.hs
+++ b/src/VeriFuzz/Parser.hs
@@ -22,6 +22,7 @@ module VeriFuzz.Parser
     )
 where
 
+import           Control.Lens
 import           Data.Functor          (($>))
 import           Data.Functor.Identity (Identity)
 import qualified Data.Text             as T
@@ -213,14 +214,24 @@ parseModList :: Parser [Identifier]
 parseModList = list <|> spaces $> []
     where list = aroundList (string "(") (string ")") ident
 
+filterDecl :: PortDir -> ModItem -> Bool
+filterDecl p (Decl (Just p') _) = p == p'
+filterDecl _ _                  = False
+
+modPorts :: PortDir -> [ModItem] -> [Port]
+modPorts p mis = filter (filterDecl p) mis ^.. traverse . declPort
+
 parseModDecl :: Parser ModDecl
 parseModDecl = do
     name    <- reserved "module" *> ident
-    modL    <- fmap defaultPort <$> parseModList
+    _       <- fmap defaultPort <$> parseModList
     _       <- symbol ";"
     modItem <- lexeme $ option [] . try $ many1 parseModItem
     _       <- reserved "endmodule"
-    return $ ModDecl name [] modL modItem
+    return $ ModDecl name
+                     (modPorts PortOut modItem)
+                     (modPorts PortIn modItem)
+                     modItem
 
 parseDescription :: Parser Description
 parseDescription = Description <$> lexeme parseModDecl