Fix imports and cabal file

3 files changed, 13 insertions, 16 deletions

diff --git a/src/Test/VeriFuzz.hs b/src/Test/VeriFuzz.hs
index 1a0b81b..8a84fd7 100644
--- a/src/Test/VeriFuzz.hs
+++ b/src/Test/VeriFuzz.hs
@@ -12,25 +12,22 @@ module Test.VeriFuzz
   (
     -- * Definitions
     module Test.VeriFuzz.Circuit
-    -- * Code Generation
-  , module Test.VeriFuzz.CodeGen
     -- * Verilog AST Data Types
-  , module Test.VeriFuzz.VerilogAST
-    -- * AST Mutation
-  , module Test.VeriFuzz.Mutate
+  , module Test.VeriFuzz.Verilog
     -- * Helpers
   , module Test.VeriFuzz.Helpers
     -- * Graphs
   , module Test.VeriFuzz.Graph.ASTGen
   , module Test.VeriFuzz.Graph.CodeGen
   , module Test.VeriFuzz.Graph.Random
+    -- * Simulator
+  , module Test.VeriFuzz.Simulator
   ) where
 
 import           Test.VeriFuzz.Circuit
-import           Test.VeriFuzz.CodeGen
 import           Test.VeriFuzz.Graph.ASTGen
 import           Test.VeriFuzz.Graph.CodeGen
 import           Test.VeriFuzz.Graph.Random
 import           Test.VeriFuzz.Helpers
-import           Test.VeriFuzz.Mutate
-import           Test.VeriFuzz.VerilogAST
+import           Test.VeriFuzz.Simulator
+import           Test.VeriFuzz.Verilog
diff --git a/src/Test/VeriFuzz/Graph/ASTGen.hs b/src/Test/VeriFuzz/Graph/ASTGen.hs
index f1ac88a..5382123 100644
--- a/src/Test/VeriFuzz/Graph/ASTGen.hs
+++ b/src/Test/VeriFuzz/Graph/ASTGen.hs
@@ -18,7 +18,7 @@ import           Data.Maybe                 (catMaybes)
 import qualified Data.Text                  as T
 import           Test.VeriFuzz.Circuit
 import           Test.VeriFuzz.Internal.Gen
-import           Test.VeriFuzz.VerilogAST
+import           Test.VeriFuzz.Verilog.AST
 
 -- | Converts a 'Node' to an 'Identifier'.
 frNode :: Node -> Identifier
@@ -73,5 +73,5 @@ genModuleDeclAST c = ModDecl id ports items
     ports = genPortsAST c
     items = genAssignAST c
 
-generateAST :: Circuit -> SourceText
-generateAST c = SourceText [Description $ genModuleDeclAST c]
+generateAST :: Circuit -> VerilogSrc
+generateAST c = VerilogSrc [Description $ genModuleDeclAST c]
diff --git a/src/Test/VeriFuzz/Helpers.hs b/src/Test/VeriFuzz/Helpers.hs
index 3650f8e..157e56c 100644
--- a/src/Test/VeriFuzz/Helpers.hs
+++ b/src/Test/VeriFuzz/Helpers.hs
@@ -13,9 +13,9 @@ Defaults and common functions.
 module Test.VeriFuzz.Helpers where
 
 import           Control.Lens
-import           Data.Text                (Text)
+import           Data.Text                 (Text)
 import qualified Data.Text
-import           Test.VeriFuzz.VerilogAST
+import           Test.VeriFuzz.Verilog.AST
 
 regDecl :: Text -> ModItem
 regDecl = Decl . Port Nothing (Just $ Reg False) . Identifier
@@ -42,8 +42,8 @@ setModName str = moduleId .~ Identifier str
 addModPort :: Port -> ModDecl -> ModDecl
 addModPort port = modPorts %~ (:) port
 
-addDescription :: Description -> SourceText -> SourceText
-addDescription desc = getSourceText %~ (:) desc
+addDescription :: Description -> VerilogSrc -> VerilogSrc
+addDescription desc = getVerilogSrc %~ (:) desc
 
 testBench :: ModDecl
 testBench =
@@ -69,5 +69,5 @@ testBench =
     ]
   ]
 
-addTestBench :: SourceText -> SourceText
+addTestBench :: VerilogSrc -> VerilogSrc
 addTestBench = addDescription $ Description testBench