Move verilog files into specific module

4 files changed, 104 insertions, 21 deletions

diff --git a/src/Test/VeriFuzz/Verilog.hs b/src/Test/VeriFuzz/Verilog.hs
new file mode 100644
index 0000000..e910d4d
--- /dev/null
+++ b/src/Test/VeriFuzz/Verilog.hs
@@ -0,0 +1,24 @@
+{-|
+Module      : Test.VeriFuzz.Verilog
+Description : The main verilog module with the syntax and code generation.
+Copyright   : (c) Yann Herklotz Grave 2018
+License     : GPL-3
+Maintainer  : ymherklotz@gmail.com
+Stability   : experimental
+Portability : POSIX
+
+The main verilog module with the syntax and code generation.
+-}
+
+module Test.VeriFuzz.Verilog
+  ( -- * AST
+    module Test.VeriFuzz.Verilog.AST
+    -- * Code Generation
+  , module Test.VeriFuzz.Verilog.CodeGen
+    -- * Verilog mutations
+  , module Test.VeriFuzz.Verilog.Mutate
+  ) where
+
+import           Test.VeriFuzz.Verilog.AST
+import           Test.VeriFuzz.Verilog.CodeGen
+import           Test.VeriFuzz.Verilog.Mutate
diff --git a/src/Test/VeriFuzz/VerilogAST.hs b/src/Test/VeriFuzz/Verilog/AST.hs
index 0497432..5f6c862 100644
--- a/src/Test/VeriFuzz/VerilogAST.hs
+++ b/src/Test/VeriFuzz/Verilog/AST.hs
@@ -1,5 +1,5 @@
 {-|
-Module      : Test.VeriFuzz.VerilogAST
+Module      : Test.VeriFuzz.Verilog.AST
 Description : Definition of the Verilog AST types.
 Copyright   : (c) Yann Herklotz Grave 2018
 License     : GPL-3
@@ -12,7 +12,7 @@ Defines the types to build a Verilog AST.
 
 {-# LANGUAGE TemplateHaskell #-}
 
-module Test.VeriFuzz.VerilogAST where
+module Test.VeriFuzz.Verilog.AST where
 
 import           Control.Lens
 import qualified Data.Graph.Inductive       as G
@@ -23,6 +23,9 @@ import qualified Test.QuickCheck            as QC
 import           Test.VeriFuzz.Circuit
 import           Test.VeriFuzz.Graph.Random
 
+class Source a where
+  genSource :: a -> Text
+
 -- | Identifier in Verilog. This is just a string of characters that can either
 -- be lowercase and uppercase for now. This might change in the future though,
 -- as Verilog supports many more characters in Identifiers.
@@ -199,7 +202,7 @@ newtype Description = Description { _getDescription :: ModDecl }
                     deriving (Show, Eq, Ord)
 
 -- | The complete sourcetext for the Verilog module.
-newtype SourceText = SourceText { _getSourceText :: [Description] }
+newtype VerilogSrc = VerilogSrc { _getVerilogSrc :: [Description] }
                    deriving (Show, Eq, Ord)
 
 -- Generate Arbitrary instances for the AST
@@ -365,8 +368,8 @@ instance QC.Arbitrary ModDecl where
 instance QC.Arbitrary Description where
   arbitrary = Description <$> QC.arbitrary
 
-instance QC.Arbitrary SourceText where
-  arbitrary = SourceText <$> QC.arbitrary
+instance QC.Arbitrary VerilogSrc where
+  arbitrary = VerilogSrc <$> QC.arbitrary
 
 -- Traversal Instance
 
@@ -380,7 +383,7 @@ traverseExpr f (CondExpr c l r)  = CondExpr <$> f c <*> f l <*> f r
 
 makeLenses ''Identifier
 makeLenses ''Number
-makeLenses ''SourceText
+makeLenses ''VerilogSrc
 makeLenses ''Description
 makeLenses ''ModDecl
 makeLenses ''ModItem
diff --git a/src/Test/VeriFuzz/CodeGen.hs b/src/Test/VeriFuzz/Verilog/CodeGen.hs
index e06891f..0247648 100644
--- a/src/Test/VeriFuzz/CodeGen.hs
+++ b/src/Test/VeriFuzz/Verilog/CodeGen.hs
@@ -1,5 +1,5 @@
 {-|
-Module      : Test.VeriFuzz.CodeGen
+Module      : Test.VeriFuzz.Verilog.CodeGen
 Description : Code generation for Verilog AST.
 Copyright   : (c) Yann Herklotz Grave 2018
 License     : GPL-3
@@ -8,10 +8,10 @@ Stability   : experimental
 Portability : POSIX
 
 This module generates the code from the Verilog AST defined in
-"Test.VeriFuzz.VerilogAST".
+"Test.VeriFuzz.Verilog.AST".
 -}
 
-module Test.VeriFuzz.CodeGen where
+module Test.VeriFuzz.Verilog.CodeGen where
 
 import           Control.Lens
 import           Data.Maybe                    (fromMaybe)
@@ -19,7 +19,7 @@ import           Data.Text                     (Text)
 import qualified Data.Text                     as T
 import qualified Data.Text.IO                  as T
 import           Test.VeriFuzz.Internal.Shared
-import           Test.VeriFuzz.VerilogAST
+import           Test.VeriFuzz.Verilog.AST
 
 showT :: (Show a) => a -> Text
 showT = T.pack . show
@@ -27,10 +27,10 @@ showT = T.pack . show
 defMap :: Maybe Statement -> Text
 defMap stat = fromMaybe ";\n" $ genStatement <$> stat
 
--- | Convert the 'SourceText' type to 'Text' so that it can be rendered.
-genSourceText :: SourceText -> Text
-genSourceText source =
-  fromList $ genDescription <$> source ^. getSourceText
+-- | Convert the 'VerilogSrc' type to 'Text' so that it can be rendered.
+genVerilogSrc :: VerilogSrc -> Text
+genVerilogSrc source =
+  fromList $ genDescription <$> source ^. getVerilogSrc
 
 -- | Generate the 'Description' to 'Text'.
 genDescription :: Description -> Text
@@ -205,3 +205,59 @@ genTask (Task name expr)
 -- | Render the 'Text' to 'IO'. This is equivalent to 'putStrLn'.
 render :: Text -> IO ()
 render = T.putStrLn
+
+-- Instances
+
+instance Source Task where
+  genSource = genTask
+
+instance Source Statement where
+  genSource = genStatement
+
+instance Source PortType where
+  genSource = genPortType
+
+instance Source ConstExpr where
+  genSource = genConstExpr
+
+instance Source RegLVal where
+  genSource = genRegLVal
+
+instance Source Delay where
+  genSource = genDelay
+
+instance Source Event where
+  genSource = genEvent
+
+instance Source Net where
+  genSource = genNet
+
+instance Source UnaryOperator where
+  genSource = genUnaryOperator
+
+instance Source Primary where
+  genSource = genPrimary
+
+instance Source Expression where
+  genSource = genExpr
+
+instance Source ContAssign where
+  genSource = genContAssign
+
+instance Source ModItem where
+  genSource = genModuleItem
+
+instance Source PortDir where
+  genSource = genPortDir
+
+instance Source Port where
+  genSource = genPort
+
+instance Source ModDecl where
+  genSource = genModuleDecl
+
+instance Source Description where
+  genSource = genDescription
+
+instance Source VerilogSrc where
+  genSource = genVerilogSrc
diff --git a/src/Test/VeriFuzz/Mutate.hs b/src/Test/VeriFuzz/Verilog/Mutate.hs
index 4712df5..b903ec9 100644
--- a/src/Test/VeriFuzz/Mutate.hs
+++ b/src/Test/VeriFuzz/Verilog/Mutate.hs
@@ -1,5 +1,5 @@
 {-|
-Module      : Test.VeriFuzz.Mutation
+Module      : Test.VeriFuzz.Verilog.Mutation
 Description : Functions to mutate the Verilog AST.
 Copyright   : (c) Yann Herklotz Grave 2018
 License     : GPL-3
@@ -7,17 +7,17 @@ Maintainer  : ymherklotz@gmail.com
 Stability   : experimental
 Portability : POSIX
 
-Functions to mutate the Verilog AST from "Test.VeriFuzz.VerilogAST" to generate
+Functions to mutate the Verilog AST from "Test.VeriFuzz.Verilog.AST" to generate
 more random patterns, such as nesting wires instead of creating new ones.
 -}
 
-module Test.VeriFuzz.Mutate where
+module Test.VeriFuzz.Verilog.Mutate where
 
 import           Control.Lens
 import           Data.Maybe                    (catMaybes, fromMaybe)
 import           Test.VeriFuzz.Internal.Gen
 import           Test.VeriFuzz.Internal.Shared
-import           Test.VeriFuzz.VerilogAST
+import           Test.VeriFuzz.Verilog.AST
 
 -- | Return if the 'Identifier' is in a 'ModDecl'.
 inPort :: Identifier -> ModDecl -> Bool
@@ -64,12 +64,12 @@ nestId id mod
     def = PrimExpr $ PrimId id
 
 -- | Replaces an identifier by a expression in all the module declaration.
-nestSource :: Identifier -> SourceText -> SourceText
+nestSource :: Identifier -> VerilogSrc -> VerilogSrc
 nestSource id src =
-  src & getSourceText . traverse . getDescription %~ nestId id
+  src & getVerilogSrc . traverse . getDescription %~ nestId id
 
 -- | Nest variables in the format @w[0-9]*@ up to a certain number.
-nestUpTo :: Int -> SourceText -> SourceText
+nestUpTo :: Int -> VerilogSrc -> VerilogSrc
 nestUpTo i src =
   foldl (flip nestSource) src $ Identifier . fromNode <$> [1..i]