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| author | Yann Herklotz <ymherklotz@gmail.com> | 2018-12-22 15:21:38 +0000 |
|---|---|---|
| committer | Yann Herklotz <ymherklotz@gmail.com> | 2018-12-22 15:22:00 +0000 |
| commit | 922e0e3cfa9b8b77f7099c2b85c2a974aa6ff948 (patch) | |
| tree | c8b6ec97869ef18f66d8c82a9e0902c8d85ca391 /src | |
| parent | 8ea1583f4b0f63a5c2b0d46594eac3955297e65c (diff) | |
| download | verismith-922e0e3cfa9b8b77f7099c2b85c2a974aa6ff948.tar.gz verismith-922e0e3cfa9b8b77f7099c2b85c2a974aa6ff948.zip | |
Format ASTGen
Diffstat (limited to 'src')
| -rw-r--r-- | src/Test/VeriFuzz/Graph/ASTGen.hs | 9 |
1 files changed, 3 insertions, 6 deletions
diff --git a/src/Test/VeriFuzz/Graph/ASTGen.hs b/src/Test/VeriFuzz/Graph/ASTGen.hs index 97b6c1c..d3e6ea5 100644 --- a/src/Test/VeriFuzz/Graph/ASTGen.hs +++ b/src/Test/VeriFuzz/Graph/ASTGen.hs @@ -62,20 +62,17 @@ genContAssignAST c (n, g) = ContAssign name <$> genAssignExpr g nodes name = frNode n genAssignAST :: Circuit -> [ContAssign] -genAssignAST c = - catMaybes $ genContAssignAST c <$> nodes +genAssignAST c = catMaybes $ genContAssignAST c <$> nodes where gr = getCircuit c nodes = G.labNodes gr genModuleDeclAST :: Circuit -> ModuleDecl -genModuleDeclAST c = - ModuleDecl id ports items +genModuleDeclAST c = ModuleDecl id ports items where id = Identifier "gen_module" ports = genPortsAST c items = Assign <$> genAssignAST c generateAST :: Circuit -> SourceText -generateAST c = - SourceText [Description $ genModuleDeclAST c] +generateAST c = SourceText [Description $ genModuleDeclAST c] |