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authorYann Herklotz Grave <git@yannherklotzgrave.com>2019-03-06 16:18:48 +0000
committerYann Herklotz Grave <git@yannherklotzgrave.com>2019-03-06 16:18:48 +0000
commit93cbc45b1ed7887af8f2c3d054f5da6b08ce9211 (patch)
treeefff053c465f94c2ad8ca8771b5cafbbe41bd58b /src
parent48e7391949db71f47b58ac20632a7b7a9447b12e (diff)
downloadverismith-93cbc45b1ed7887af8f2c3d054f5da6b08ce9211.tar.gz
verismith-93cbc45b1ed7887af8f2c3d054f5da6b08ce9211.zip
Fix positive arbitrary generation
Diffstat (limited to 'src')
-rw-r--r--src/VeriFuzz/AST.hs2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/VeriFuzz/AST.hs b/src/VeriFuzz/AST.hs
index a2ebb32..d37b053 100644
--- a/src/VeriFuzz/AST.hs
+++ b/src/VeriFuzz/AST.hs
@@ -131,7 +131,7 @@ import Data.Traversable (sequenceA)
import qualified Test.QuickCheck as QC
positiveArb :: (QC.Arbitrary a, Ord a, Num a) => QC.Gen a
-positiveArb = QC.suchThat QC.arbitrary (> 0)
+positiveArb = abs <$> QC.suchThat QC.arbitrary (/= 0)
-- | Identifier in Verilog. This is just a string of characters that can either
-- be lowercase and uppercase for now. This might change in the future though,