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author | Yann Herklotz <ymherklotz@gmail.com> | 2019-01-01 15:24:42 +0100 |
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committer | Yann Herklotz <ymherklotz@gmail.com> | 2019-01-01 15:24:42 +0100 |
commit | 1b223cb1afc692468c0956796944b582dd2c4751 (patch) | |
tree | aff077407c41759d4fcc1e5125efa852e6e7bd68 /src | |
parent | a6ccd5a6b0d6206cc2798631b139f9fc27c311ac (diff) | |
download | verismith-1b223cb1afc692468c0956796944b582dd2c4751.tar.gz verismith-1b223cb1afc692468c0956796944b582dd2c4751.zip |
Add monoid instance for LVal
Diffstat (limited to 'src')
-rw-r--r-- | src/Test/VeriFuzz/Verilog/AST.hs | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/src/Test/VeriFuzz/Verilog/AST.hs b/src/Test/VeriFuzz/Verilog/AST.hs index 965f6e3..b643db5 100644 --- a/src/Test/VeriFuzz/Verilog/AST.hs +++ b/src/Test/VeriFuzz/Verilog/AST.hs @@ -71,6 +71,15 @@ data LVal = RegId Identifier | RegConcat { _regConc :: [Expr] } deriving (Eq) +instance Semigroup LVal where + (RegConcat a) <> (RegConcat b) = RegConcat $ a <> b + (RegConcat a) <> b = RegConcat $ a <> [b] + a <> (RegConcat b) = RegConcat $ a : b + a <> b = RegConcat [a, b] + +instance Monoid LVal where + mempty = RegConcat [] + -- | Binary operators that are currently supported in the verilog generation. data BinaryOperator = BinPlus -- ^ @+@ | BinMinus -- ^ @-@ @@ -115,7 +124,7 @@ data UnaryOperator = UnPlus -- ^ @+@ -- | Verilog expression, which can either be a primary expression, unary -- expression, binary operator expression or a conditional expression. data Expr = Number { _numSize :: Int - , _numVal :: Int + , _numVal :: Integer } | Id { _exprId :: Identifier } | Concat { _concatExpr :: [Expr] } |