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author | Yann Herklotz <ymherklotz@gmail.com> | 2019-01-10 17:48:43 +0000 |
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committer | Yann Herklotz <ymherklotz@gmail.com> | 2019-01-10 17:48:43 +0000 |
commit | fe85c15c4a4dae8fa88f74472e6b42b31b17e2a1 (patch) | |
tree | 96ead073098c497b56d7bcf9abe6891ac18b2f2f /src | |
parent | eb598f451b882f56ed3648ebc8d25ee494f9bfa9 (diff) | |
download | verismith-fe85c15c4a4dae8fa88f74472e6b42b31b17e2a1.tar.gz verismith-fe85c15c4a4dae8fa88f74472e6b42b31b17e2a1.zip |
Add render to test
Diffstat (limited to 'src')
-rw-r--r-- | src/VeriFuzz/Verilog/Mutate.hs | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/VeriFuzz/Verilog/Mutate.hs b/src/VeriFuzz/Verilog/Mutate.hs index 36cdb9b..e7bb199 100644 --- a/src/VeriFuzz/Verilog/Mutate.hs +++ b/src/VeriFuzz/Verilog/Mutate.hs @@ -87,7 +87,7 @@ allVars mod = -- it to the body of the second module. It first has to make all the inputs into -- @reg@. -- --- >>> instantiateMod mod main +-- >>> render $ instantiateMod mod main -- module main; -- wire [4:0] y; -- reg [4:0] x; @@ -107,7 +107,7 @@ instantiateMod mod main = -- | Instantiate without adding wire declarations. It also does not count the -- current instantiations of the same module. -- --- >>> instantiateMod_ mod +-- >>> render $ instantiateMod_ mod -- m m(y, x); -- <BLANKLINE> instantiateMod_ :: ModDecl -> ModItem @@ -119,7 +119,7 @@ instantiateMod_ mod = -- | Initialise all the inputs and outputs to a module. -- --- >>> initMod mod +-- >>> render $ initMod mod -- module m(y, x); -- output wire [4:0] y; -- input wire [4:0] x; |