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| author | Yann Herklotz <ymherklotz@gmail.com> | 2018-12-01 18:04:57 +0000 |
|---|---|---|
| committer | Yann Herklotz <ymherklotz@gmail.com> | 2018-12-01 18:04:57 +0000 |
| commit | 2c46f7c0700878eddd1b761332373f6d97dea11e (patch) | |
| tree | 9f36fff1b888bba2f1e26add20807557856ec76c /src | |
| parent | 1d09a78b726827667e342cb3ede8253cc83d8ec1 (diff) | |
| download | verismith-2c46f7c0700878eddd1b761332373f6d97dea11e.tar.gz verismith-2c46f7c0700878eddd1b761332373f6d97dea11e.zip | |
Fix typo
Diffstat (limited to 'src')
| -rw-r--r-- | src/Test/VeriFuzz/CodeGen.hs | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/Test/VeriFuzz/CodeGen.hs b/src/Test/VeriFuzz/CodeGen.hs index 27457e3..eb99d6b 100644 --- a/src/Test/VeriFuzz/CodeGen.hs +++ b/src/Test/VeriFuzz/CodeGen.hs @@ -22,7 +22,7 @@ genModuleDecl mod = "module " <> mod ^. moduleId . getIdentifier <> "(\n" <> ports <> "\n);\n" <> modItems - <> "endomodule\n" + <> "endmodule\n" where ports = sep ",\n" $ genPort <$> mod ^. modPorts modItems = fromList $ genModuleItem <$> mod ^. moduleItems |