diff options
| author | Yann Herklotz <ymherklotz@gmail.com> | 2018-12-27 14:41:46 +0100 |
|---|---|---|
| committer | Yann Herklotz <ymherklotz@gmail.com> | 2018-12-27 14:41:46 +0100 |
| commit | b0975b12e655eb5c3920f7be2fa6ac57e18317bf (patch) | |
| tree | 1a44c4f065f0a926173b027a5623affbd5df9992 /src | |
| parent | 7fd3ca2523c6edad38a7f4148628ba6bd3994942 (diff) | |
| download | verismith-b0975b12e655eb5c3920f7be2fa6ac57e18317bf.tar.gz verismith-b0975b12e655eb5c3920f7be2fa6ac57e18317bf.zip | |
Add instantiation function
Diffstat (limited to 'src')
| -rw-r--r-- | src/Test/VeriFuzz/Mutate.hs | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/src/Test/VeriFuzz/Mutate.hs b/src/Test/VeriFuzz/Mutate.hs index 6dad043..4712df5 100644 --- a/src/Test/VeriFuzz/Mutate.hs +++ b/src/Test/VeriFuzz/Mutate.hs @@ -11,8 +11,6 @@ Functions to mutate the Verilog AST from "Test.VeriFuzz.VerilogAST" to generate more random patterns, such as nesting wires instead of creating new ones. -} -{-# LANGUAGE OverloadedStrings #-} - module Test.VeriFuzz.Mutate where import Control.Lens @@ -70,6 +68,13 @@ nestSource :: Identifier -> SourceText -> SourceText nestSource id src = src & getSourceText . traverse . getDescription %~ nestId id +-- | Nest variables in the format @w[0-9]*@ up to a certain number. nestUpTo :: Int -> SourceText -> SourceText nestUpTo i src = foldl (flip nestSource) src $ Identifier . fromNode <$> [1..i] + +-- | Add a Module Instantiation using 'ModInst' from the first module passed to +-- it to the body of the second module. +instantiateMod :: ModDecl -> ModDecl -> ModDecl +instantiateMod mod main = + main |