aboutsummaryrefslogtreecommitdiffstats
path: root/test/Property.hs
diff options
context:
space:
mode:
authorYann Herklotz <git@yannherklotz.com>2019-05-20 12:51:26 +0100
committerYann Herklotz <git@yannherklotz.com>2019-05-20 12:51:26 +0100
commita6c69c67a9d3923443fccad77293c365f4bbc0d3 (patch)
tree8e11bec1a75f80a7fbbd713b6867c7ad2ba086cb /test/Property.hs
parentb72c905c718ff52e623b748034d567cf8552b50e (diff)
parent9a051648695d459d4564be58ae4850e159cb3ba3 (diff)
downloadverismith-a6c69c67a9d3923443fccad77293c365f4bbc0d3.tar.gz
verismith-a6c69c67a9d3923443fccad77293c365f4bbc0d3.zip
Merge branch 'master' of github.com:ymherklotz/verifuzz
Diffstat (limited to 'test/Property.hs')
-rw-r--r--test/Property.hs17
1 files changed, 12 insertions, 5 deletions
diff --git a/test/Property.hs b/test/Property.hs
index 7b1771c..001c7d3 100644
--- a/test/Property.hs
+++ b/test/Property.hs
@@ -32,11 +32,18 @@ import VeriFuzz.Verilog.Parser
randomDAG' :: Gen Circuit
randomDAG' = Hog.resize 30 randomDAG
-simpleGraph :: Property
-simpleGraph = Hog.property $ do
+acyclicGraph :: Property
+acyclicGraph = Hog.property $ do
xs <- Hog.forAllWith (const "") randomDAG'
Hog.assert $ simp xs
- where simp = G.isSimple . getCircuit
+ where
+ simp g =
+ (== G.noNodes (getCircuit g))
+ . sum
+ . fmap length
+ . G.scc
+ . getCircuit
+ $ g
type GenFunctor f a b c =
( Functor f
@@ -76,7 +83,7 @@ propertyResultInterrupted = do
propertyTests :: TestTree
propertyTests = testGroup
"Property Tests"
- [ testProperty "simple graph generation check" simpleGraph
- , testProperty "fmap for Result" propertyResultInterrupted
+ [ testProperty "acyclic graph generation check" acyclicGraph
+ , testProperty "fmap for Result" propertyResultInterrupted
, parserTests
]