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author | Yann Herklotz <git@yannherklotz.com> | 2019-07-21 13:37:25 +0200 |
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committer | Yann Herklotz <git@yannherklotz.com> | 2019-07-21 13:37:25 +0200 |
commit | 30fbe26f59e54a276f88650ffa5e78343b5411eb (patch) | |
tree | aa3166c423f262ee6296826d2c815a0b54084c31 /test/Reduce.hs | |
parent | b5c035e45949945cc62845fa6492cffa77992524 (diff) | |
parent | c19a51a8156bbcaee13d9819c8fe54ed0ca5c4cc (diff) | |
download | verismith-30fbe26f59e54a276f88650ffa5e78343b5411eb.tar.gz verismith-30fbe26f59e54a276f88650ffa5e78343b5411eb.zip |
Merge branch 'master' into fix/resize-modports
Diffstat (limited to 'test/Reduce.hs')
-rw-r--r-- | test/Reduce.hs | 97 |
1 files changed, 96 insertions, 1 deletions
diff --git a/test/Reduce.hs b/test/Reduce.hs index 9c59e48..bc47d94 100644 --- a/test/Reduce.hs +++ b/test/Reduce.hs @@ -17,7 +17,7 @@ module Reduce ) where -import Data.List ((\\)) +import Data.List ( (\\) ) import Test.Tasty import Test.Tasty.HUnit import VeriFuzz @@ -29,6 +29,7 @@ reduceUnitTests = testGroup [ moduleReducerTest , modItemReduceTest , halveStatementsTest + , statementReducerTest , activeWireTest , cleanTest , cleanAllTest @@ -52,6 +53,7 @@ module top; reg h; wire i; wire j; + wire clk; initial d <= a; always @* begin @@ -62,6 +64,8 @@ module top; end end + always @(posedge clk); + assign b = g; endmodule |] @@ -74,6 +78,7 @@ module top; reg f; reg g; reg h; + wire clk; initial d <= a; always @* begin @@ -84,6 +89,8 @@ module top; end end + always @(posedge clk); + assign b = g; endmodule |] @@ -366,6 +373,94 @@ endmodule |]) -- brittany-disable-next-binding +statementReducerTest :: TestTree +statementReducerTest = testCase "Statement reducer" $ do + GenVerilog <$> halveStatements "top" srcInfo1 @?= fmap GenVerilog golden1 + GenVerilog <$> halveStatements "top" srcInfo2 @?= fmap GenVerilog golden2 + where + srcInfo1 = SourceInfo "top" [verilog| +module top(y, x); + output wire [4:0] y; + input wire [4:0] x; + + always @(posedge clk) begin + a <= 1; + b <= 2; + c <= 3; + d <= 4; + end + + always @(posedge clk) begin + a <= 1; + b <= 2; + c <= 3; + d <= 4; + end +endmodule +|] + golden1 = Dual (SourceInfo "top" [verilog| +module top(y, x); + output wire [4:0] y; + input wire [4:0] x; + + always @(posedge clk) begin + a <= 1; + b <= 2; + end + + always @(posedge clk) begin + a <= 1; + b <= 2; + end +endmodule +|]) $ SourceInfo "top" [verilog| +module top(y, x); + output wire [4:0] y; + input wire [4:0] x; + + always @(posedge clk) begin + c <= 3; + d <= 4; + end + + always @(posedge clk) begin + c <= 3; + d <= 4; + end +endmodule +|] + srcInfo2 = SourceInfo "top" [verilog| +module top(y, x); + output wire [4:0] y; + input wire [4:0] x; + + always @(posedge clk) begin + if (x) + y <= 2; + else + y <= 3; + end +endmodule +|] + golden2 = Dual (SourceInfo "top" [verilog| +module top(y, x); + output wire [4:0] y; + input wire [4:0] x; + + always @(posedge clk) + y <= 2; +endmodule +|]) $ SourceInfo "top" [verilog| +module top(y, x); + output wire [4:0] y; + input wire [4:0] x; + + always @(posedge clk) + y <= 3; +endmodule +|] + +-- brittany-disable-next-binding moduleReducerTest :: TestTree moduleReducerTest = testCase "Module reducer" $ do halveModules srcInfo1 @?= golden1 |