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author | Yann Herklotz <git@ymhg.org> | 2019-05-11 22:14:42 +0100 |
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committer | Yann Herklotz <git@ymhg.org> | 2019-05-11 22:14:42 +0100 |
commit | 9637980a562d79582689daa5dff43814a531f900 (patch) | |
tree | 311fba411d26af930b1662f42c9648a48326c2d5 /test/Reduce.hs | |
parent | 6218c8fd0f7dae36bda08fd2b132901e4707584a (diff) | |
download | verismith-9637980a562d79582689daa5dff43814a531f900.tar.gz verismith-9637980a562d79582689daa5dff43814a531f900.zip |
Implement module item reduction properly
Diffstat (limited to 'test/Reduce.hs')
-rw-r--r-- | test/Reduce.hs | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/test/Reduce.hs b/test/Reduce.hs index 7db948b..5afae18 100644 --- a/test/Reduce.hs +++ b/test/Reduce.hs @@ -57,7 +57,7 @@ endmodule modItemReduceTest :: TestTree modItemReduceTest = testCase "Module items" $ do - halveModItems srcInfo1 @?= golden1 + GenVerilog <$> halveModItems srcInfo1 @?= golden1 where srcInfo1 = SourceInfo "top" [verilog| module top(y, x); @@ -70,25 +70,25 @@ module top(y, x); assign y = w; endmodule |] - golden1 = Dual (SourceInfo "top" [verilog| + golden1 = GenVerilog <$> Dual (SourceInfo "top" [verilog| module top(y, x); input x; output y; wire z; wire w; + assign y = 1'b0; assign z = x; - assign y = w; endmodule -|]) $ SourceInfo "top" [verilog| +|]) (SourceInfo "top" [verilog| module top(y, x); input x; output y; wire z; wire w; - assign w = 1'b0; assign y = w; + assign w = 1'b0; endmodule -|] +|]) moduleReducerTest :: TestTree moduleReducerTest = testCase "Module reducer" $ do |