Add tests for new generation method

2 files changed, 16 insertions, 13 deletions

diff --git a/tests/Property.hs b/tests/Property.hs
index 55b7f31..2c06474 100644
--- a/tests/Property.hs
+++ b/tests/Property.hs
@@ -2,20 +2,32 @@ module Property (propertyTests) where
 
 import           Data.Graph.Inductive
 import           Test.Tasty
-import           Test.Tasty.QuickCheck as QC
+import qualified Test.Tasty.QuickCheck         as QC
 import           Test.VeriFuzz
+import qualified Test.VeriFuzz.Graph.RandomAlt as V
 
 newtype TestGraph = TestGraph { getGraph :: Gr Gate () }
                   deriving (Show)
 
+newtype AltTestGraph = AltTestGraph { getAltGraph :: Gr Gate () }
+                  deriving (Show)
+
 instance QC.Arbitrary TestGraph where
-  arbitrary = TestGraph <$> randomDAG 30
+  arbitrary = TestGraph <$> QC.resize 30 randomDAG
 
-simpleGraph = QC.testProperty "simple graph generation" $
-  \graph -> simp (graph :: TestGraph)
+instance QC.Arbitrary AltTestGraph where
+  arbitrary = AltTestGraph <$> QC.resize 100 V.randomDAG
+
+simpleGraph = QC.testProperty "simple graph generation check" $
+  \graph -> simp graph
   where simp = isSimple . getGraph
 
+simpleAltGraph = QC.testProperty "simple alternative graph generation check" $
+  \graph -> simp graph
+  where simp = isSimple . getAltGraph
+
 propertyTests :: TestTree
 propertyTests = testGroup "Property Tests"
   [ simpleGraph
+  , simpleAltGraph
   ]
diff --git a/tests/Unit.hs b/tests/Unit.hs
index 67f642c..de4fa16 100644
--- a/tests/Unit.hs
+++ b/tests/Unit.hs
@@ -38,12 +38,3 @@ trans e =
                               PrimExpr . PrimId $ Identifier "Replaced"
                             else PrimExpr (PrimId id)
     _                    -> e
-
-runMain = do
-  gr <- genRandomDAG 100 :: IO (G.Gr Gate ())
---  _ <- runGraphviz (graphToDot quickParams $ emap (const "") gr) Png "output.png",
---  T.putStrLn $ generate gr
-  --g <- QC.generate (QC.arbitrary :: QC.Gen VerilogSrc)
-  let x = generateAST $ Circuit gr
-  let y = head . reverse $ x ^.. getVerilogSrc . traverse . getDescription . moduleItems . traverse . _ModCA . contAssignExpr
-  print $ transformOf traverseExpr trans y