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| author | Yann Herklotz <ymherklotz@gmail.com> | 2018-12-25 13:21:16 +0100 |
|---|---|---|
| committer | Yann Herklotz <ymherklotz@gmail.com> | 2018-12-25 13:21:16 +0100 |
| commit | 6a8417a833b5c1b56bb777214f7800ea81684615 (patch) | |
| tree | 7f69c483f29d7a914c84aec769d3fa3ac71114a1 /tests | |
| parent | ffd032f74a8eed1c47a93d7ce619734580e1ae61 (diff) | |
| download | verismith-6a8417a833b5c1b56bb777214f7800ea81684615.tar.gz verismith-6a8417a833b5c1b56bb777214f7800ea81684615.zip | |
Fix tests with ContAssign
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/Unit.hs | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/Unit.hs b/tests/Unit.hs index 976f23b..318150b 100644 --- a/tests/Unit.hs +++ b/tests/Unit.hs @@ -47,5 +47,5 @@ runMain = do -- T.putStrLn $ generate gr --g <- QC.generate (QC.arbitrary :: QC.Gen SourceText) let x = generateAST $ Circuit gr - let y = head . reverse $ x ^.. getSourceText . traverse . getDescription . moduleItems . traverse . _Assign . contAssignExpr + let y = head . reverse $ x ^.. getSourceText . traverse . getDescription . moduleItems . traverse . _ContAssign . contAssignExpr print $ transformOf traverseExpr trans y |