diff options
-rw-r--r-- | .gitignore | 5 | ||||
-rw-r--r-- | app/Main.hs | 10 | ||||
-rw-r--r-- | src/VeriFuzz.hs | 53 | ||||
-rw-r--r-- | src/VeriFuzz/Config.hs | 50 | ||||
-rw-r--r-- | src/VeriFuzz/Fuzz.hs | 8 | ||||
-rw-r--r-- | src/VeriFuzz/Reduce.hs | 12 | ||||
-rw-r--r-- | src/VeriFuzz/Report.hs | 7 | ||||
-rw-r--r-- | src/VeriFuzz/Verilog/Gen.hs | 37 | ||||
-rw-r--r-- | test/Property.hs | 2 | ||||
-rw-r--r-- | verifuzz.cabal | 8 |
10 files changed, 110 insertions, 82 deletions
@@ -1,7 +1,10 @@ # Files TAGS +*.jou +*.log # Folders .stack-work .shelly -failed
\ No newline at end of file +failed +output* diff --git a/app/Main.hs b/app/Main.hs index 8da1151..861fcd0 100644 --- a/app/Main.hs +++ b/app/Main.hs @@ -193,9 +193,13 @@ argparse = <> metavar "config" ) +version :: Parser (a -> a) +version = infoOption V.versionInfo $ mconcat + [long "version", short 'v', help "Show version information.", hidden] + opts :: ParserInfo Opts opts = info - (argparse <**> helper) + (argparse <**> helper <**> version) ( fullDesc <> progDesc "Fuzz different simulators and synthesisers." <> header @@ -206,7 +210,7 @@ getConfig :: Maybe FilePath -> IO V.Config getConfig = maybe (return V.defaultConfig) V.parseConfigFile handleOpts :: Opts -> IO () -handleOpts (Fuzz out configF _ _ n) = do +handleOpts (Fuzz _ configF _ _ n) = do config <- getConfig configF _ <- V.runFuzz config V.defaultYosys @@ -216,7 +220,7 @@ handleOpts (Generate f c) = do config <- getConfig c source <- V.proceduralIO "top" config maybe (T.putStrLn $ V.genSource source) - (flip T.writeFile (V.genSource source)) + (flip T.writeFile $ V.genSource source) f handleOpts (Parse f) = do verilogSrc <- readFile file diff --git a/src/VeriFuzz.hs b/src/VeriFuzz.hs index e844f57..84d3336 100644 --- a/src/VeriFuzz.hs +++ b/src/VeriFuzz.hs @@ -8,11 +8,14 @@ Stability : experimental Portability : POSIX -} +{-# LANGUAGE TemplateHaskell #-} + module VeriFuzz ( runEquivalence , runSimulation , runReduce , draw + , versionInfo , SourceInfo(..) , module VeriFuzz.Verilog , module VeriFuzz.Config @@ -24,28 +27,26 @@ module VeriFuzz where import Control.Lens -import Control.Monad.IO.Class (MonadIO) -import Control.Monad.Trans.Maybe (runMaybeT) -import qualified Crypto.Random.DRBG as C -import Data.ByteString (ByteString) -import Data.ByteString.Builder (byteStringHex, toLazyByteString) -import qualified Data.ByteString.Lazy as L -import qualified Data.Graph.Inductive as G -import qualified Data.Graph.Inductive.Dot as G -import Data.Maybe (isNothing) -import Data.Text (Text) -import qualified Data.Text as T -import Data.Text.Encoding (decodeUtf8) -import qualified Data.Text.IO as T -import Hedgehog (Gen) -import qualified Hedgehog.Gen as Hog -import qualified Hedgehog.Internal.Gen as Hog -import Hedgehog.Internal.Seed (Seed) -import qualified Hedgehog.Internal.Seed as Hog -import qualified Hedgehog.Internal.Tree as Hog -import Prelude hiding (FilePath) +import qualified Crypto.Random.DRBG as C +import Data.ByteString (ByteString) +import Data.ByteString.Builder (byteStringHex, toLazyByteString) +import qualified Data.ByteString.Lazy as L +import qualified Data.Graph.Inductive as G +import qualified Data.Graph.Inductive.Dot as G +import Data.Maybe (isNothing) +import Data.Text (Text) +import qualified Data.Text as T +import Data.Text.Encoding (decodeUtf8) +import qualified Data.Text.IO as T +import Data.Version (showVersion) +import Development.GitRev +import Hedgehog (Gen) +import qualified Hedgehog.Gen as Hog +import Hedgehog.Internal.Seed (Seed) +import Paths_verifuzz (version) +import Prelude hiding (FilePath) import Shelly -import Shelly.Lifted (liftSh) +import Shelly.Lifted (liftSh) import VeriFuzz.Circuit import VeriFuzz.Config import VeriFuzz.Fuzz @@ -56,6 +57,16 @@ import VeriFuzz.Sim import VeriFuzz.Sim.Internal import VeriFuzz.Verilog +versionInfo :: String +versionInfo = + "VeriFuzz " + <> showVersion version + <> " (" + <> $(gitCommitDate) + <> " " + <> $(gitHash) + <> ")" + -- | Generate a specific number of random bytestrings of size 256. randomByteString :: C.CtrDRBG -> Int -> [ByteString] -> [ByteString] randomByteString gen n bytes diff --git a/src/VeriFuzz/Config.hs b/src/VeriFuzz/Config.hs index fa06e46..6c0d058 100644 --- a/src/VeriFuzz/Config.hs +++ b/src/VeriFuzz/Config.hs @@ -74,14 +74,13 @@ module VeriFuzz.Config ) where -import Control.Applicative (Alternative, (<|>)) +import Control.Applicative (Alternative) import Control.Lens hiding ((.=)) import Data.List.NonEmpty (NonEmpty (..)) import Data.Maybe (fromMaybe) import Data.Text (Text) import qualified Data.Text.IO as T import Hedgehog.Internal.Seed (Seed) -import qualified Hedgehog.Internal.Seed as Seed import Toml (TomlCodec, (.=)) import qualified Toml @@ -129,25 +128,26 @@ import qualified Toml -- >>> T.putStrLn $ encodeConfig defaultConfig -- <BLANKLINE> -- [probability] --- eventlist.all = 1 +-- eventlist.all = 0 -- eventlist.clk = 1 -- eventlist.var = 1 --- expr.binary = 1 --- expr.concatenation = 1 +-- expr.binary = 5 +-- expr.concatenation = 3 -- expr.number = 1 --- expr.signed = 1 +-- expr.rangeselect = 5 +-- expr.signed = 5 -- expr.string = 0 --- expr.ternary = 1 --- expr.unary = 1 --- expr.unsigned = 1 --- expr.variable = 1 +-- expr.ternary = 5 +-- expr.unary = 5 +-- expr.unsigned = 5 +-- expr.variable = 5 -- moditem.always = 1 -- moditem.assign = 5 -- moditem.instantiation = 1 -- statement.blocking = 0 -- statement.conditional = 1 -- statement.forloop = 1 --- statement.nonblocking = 15 +-- statement.nonblocking = 3 -- <BLANKLINE> -- [property] -- module.depth = 2 @@ -268,10 +268,30 @@ defaultConfig = Config [] [SynthDescription "yosys", SynthDescription "vivado"] where - defModItem = ProbModItem 5 1 1 - defStmnt = ProbStatement 0 15 1 1 - defExpr = ProbExpr 1 1 1 1 1 1 1 0 1 1 - defEvent = ProbEventList 1 1 1 + defModItem = + ProbModItem 5 -- Assign + 1 -- Always + 1 -- Instantiation + defStmnt = + ProbStatement 0 -- Blocking assignment + 3 -- Non-blocking assignment + 1 -- Conditional + 1 -- For loop + defExpr = + ProbExpr 1 -- Number + 5 -- Identifier + 5 -- Range selection + 5 -- Unary operator + 5 -- Binary operator + 5 -- Ternary conditional + 3 -- Concatenation + 0 -- String + 5 -- Signed function + 5 -- Unsigned funtion + defEvent = + ProbEventList 0 -- All + 1 -- Clk + 0 -- Var twoKey :: Toml.Piece -> Toml.Piece -> Toml.Key twoKey a b = Toml.Key (a :| [b]) diff --git a/src/VeriFuzz/Fuzz.hs b/src/VeriFuzz/Fuzz.hs index 57928b4..553fc88 100644 --- a/src/VeriFuzz/Fuzz.hs +++ b/src/VeriFuzz/Fuzz.hs @@ -33,16 +33,12 @@ import Control.Monad.Trans.Control (MonadBaseControl) import Control.Monad.Trans.Maybe (runMaybeT) import Control.Monad.Trans.Reader hiding (local) import Control.Monad.Trans.State.Strict -import Data.ByteString (ByteString) import Data.List (nubBy) import Data.Maybe (isNothing) import Data.Text (Text) import qualified Data.Text as T import Data.Time import Hedgehog (Gen) -import Hedgehog (Gen) -import qualified Hedgehog.Gen as Hog -import qualified Hedgehog.Gen as Hog import qualified Hedgehog.Internal.Gen as Hog import Hedgehog.Internal.Seed (Seed) import qualified Hedgehog.Internal.Seed as Hog @@ -54,11 +50,7 @@ import VeriFuzz.Config import VeriFuzz.Internal import VeriFuzz.Report import VeriFuzz.Result -import VeriFuzz.Sim.Icarus import VeriFuzz.Sim.Internal -import VeriFuzz.Sim.Quartus -import VeriFuzz.Sim.Vivado -import VeriFuzz.Sim.XST import VeriFuzz.Sim.Yosys import VeriFuzz.Verilog.AST import VeriFuzz.Verilog.CodeGen diff --git a/src/VeriFuzz/Reduce.hs b/src/VeriFuzz/Reduce.hs index e666f38..49d4dc9 100644 --- a/src/VeriFuzz/Reduce.hs +++ b/src/VeriFuzz/Reduce.hs @@ -102,12 +102,12 @@ cleanMod m newm = modify . change <$> newm $ l ^. modItems -halveStatements :: Statement -> Replacement Statement -halveStatements (SeqBlock l ) = SeqBlock <$> halve l -halveStatements (CondStmnt _ (Just a) b) = maybe (Single a) (Dual a) b -halveStatements (CondStmnt _ Nothing b) = maybe None Single b -halveStatements (ForLoop _ _ _ s ) = Single s -halveStatements _ = None +-- halveStatements :: Statement -> Replacement Statement +-- halveStatements (SeqBlock l ) = SeqBlock <$> halve l +-- halveStatements (CondStmnt _ (Just a) b) = maybe (Single a) (Dual a) b +-- halveStatements (CondStmnt _ Nothing b) = maybe None Single b +-- halveStatements (ForLoop _ _ _ s ) = Single s +-- halveStatements _ = None -- | Split a module declaration in half by trying to remove assign statements. halveAssigns :: SourceInfo -> Replacement SourceInfo diff --git a/src/VeriFuzz/Report.hs b/src/VeriFuzz/Report.hs index aab318c..15f695d 100644 --- a/src/VeriFuzz/Report.hs +++ b/src/VeriFuzz/Report.hs @@ -31,11 +31,8 @@ module VeriFuzz.Report where import Control.Lens -import Control.Monad.IO.Class -import Control.Monad.Trans.Control (MonadBaseControl) -import Data.ByteString (ByteString) -import Prelude hiding (FilePath) -import Shelly.Lifted (MonadSh) +import Data.ByteString (ByteString) +import Prelude hiding (FilePath) import VeriFuzz.Config import VeriFuzz.Result import VeriFuzz.Sim.Icarus diff --git a/src/VeriFuzz/Verilog/Gen.hs b/src/VeriFuzz/Verilog/Gen.hs index 33413f2..7b9c31b 100644 --- a/src/VeriFuzz/Verilog/Gen.hs +++ b/src/VeriFuzz/Verilog/Gen.hs @@ -250,22 +250,20 @@ makeIdentifier prefix = do return ident getPort' :: PortType -> Identifier -> [Port] -> StateGen Port -getPort' pt i c = - case filter portId c of - x:_ -> return x - [] -> newPort i pt - where - portId (Port pt' _ _ i') = i == i' && pt == pt' +getPort' pt i c = case filter portId c of + x : _ -> return x + [] -> newPort i pt + where portId (Port pt' _ _ i') = i == i' && pt == pt' nextPort :: PortType -> StateGen Port nextPort pt = do context <- get - ident <- makeIdentifier . T.toLower $ showT pt + ident <- makeIdentifier . T.toLower $ showT pt getPort' pt ident (_variables context) newPort :: Identifier -> PortType -> StateGen Port newPort ident pt = do - p <- gen $ Port pt <$> Hog.bool <*> range <*> pure ident + p <- gen $ Port pt <$> Hog.bool <*> range <*> pure ident variables %= (p :) return p @@ -309,13 +307,14 @@ seqBlock = do conditional :: StateGen Statement conditional = do expr <- scopedExpr - nc <- _nameCounter <$> get + nc <- _nameCounter <$> get tstat <- seqBlock + nc' <- _nameCounter <$> get nameCounter .= nc - fstat <- Hog.maybe seqBlock - nc' <- _nameCounter <$> get - nameCounter .= max nc nc' - return $ CondStmnt expr (Just tstat) fstat + fstat <- seqBlock + nc'' <- _nameCounter <$> get + nameCounter .= max nc' nc'' + return $ CondStmnt expr (Just tstat) (Just fstat) --constToExpr :: ConstExpr -> Expr --constToExpr (ConstNum s n ) = Number s n @@ -329,12 +328,12 @@ conditional = do forLoop :: StateGen Statement forLoop = do - num <- Hog.int (Hog.linear 0 20) - var <- lvalFromPort <$> nextPort Reg + num <- Hog.int (Hog.linear 0 20) + var <- lvalFromPort <$> nextPort Reg ForLoop (Assign var Nothing 0) - (BinOp (varId var) BinLT $ fromIntegral num) - (Assign var Nothing $ BinOp (varId var) BinPlus 1) - <$> seqBlock + (BinOp (varId var) BinLT $ fromIntegral num) + (Assign var Nothing $ BinOp (varId var) BinPlus 1) + <$> seqBlock where varId v = Id (v ^. regId) statement :: StateGen Statement @@ -353,7 +352,7 @@ statement = do recEventList :: NonEmpty Identifier -> Hog.Size -> Gen Event recEventList ids size | size <= 0 = idgen - | size > 0 = Hog.choice [idgen, EOr <$> recCall <*> recCall] + | otherwise = Hog.choice [idgen, EOr <$> recCall <*> recCall] where idgen = fmap EId . Hog.element $ toList ids recCall = recEventList ids (size `div` 2) diff --git a/test/Property.hs b/test/Property.hs index f7c6865..fe802c9 100644 --- a/test/Property.hs +++ b/test/Property.hs @@ -23,7 +23,7 @@ import qualified Hedgehog.Range as Hog import Test.Tasty import Test.Tasty.Hedgehog import Text.Parsec -import VeriFuzz +import VeriFuzz hiding (Property) import VeriFuzz.Result import VeriFuzz.Verilog.Lex import VeriFuzz.Verilog.Parser diff --git a/verifuzz.cabal b/verifuzz.cabal index 6137f0b..9f63c17 100644 --- a/verifuzz.cabal +++ b/verifuzz.cabal @@ -1,5 +1,5 @@ name: verifuzz -version: 0.1.1.0 +version: 0.2.0.0 synopsis: Random verilog generation and simulator testing. description: VeriFuzz provides random verilog generation modules @@ -26,6 +26,7 @@ library hs-source-dirs: src default-language: Haskell2010 build-tools: alex >=3 && <4 + other-modules: Paths_verifuzz exposed-modules: VeriFuzz , VeriFuzz.Circuit , VeriFuzz.Circuit.Base @@ -83,6 +84,7 @@ library , time >= 1.8.0.2 && <1.9 , lifted-base >=0.2.3 && <0.3 , monad-control >=1.0.2 && <1.1 + , gitrev >= 1.3.1 && <1.4 default-extensions: OverloadedStrings executable verifuzz @@ -92,7 +94,7 @@ executable verifuzz ghc-options: -threaded build-depends: base >= 4.7 && < 5 , shelly >=1.8.0 && <1.9 - , verifuzz >= 0.1 && <0.2 + , verifuzz , text >=1.2 && <1.3 , bytestring >=0.10 && <0.11 , optparse-applicative >=0.14 && <0.15 @@ -106,7 +108,7 @@ test-suite verifuzz-test other-modules: Unit , Property build-depends: base >=4 && <5 - , verifuzz >=0.1 && <0.2 + , verifuzz , fgl >=5.7 && <5.8 , tasty >=1.2 && <1.3 , tasty-hunit >=0.10 && <0.11 |