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-rw-r--r-- | .gitignore | 3 |
1 files changed, 2 insertions, 1 deletions
@@ -5,4 +5,5 @@ TAGS .stack-work .shelly equiv* -output*
\ No newline at end of file +output* +failed
\ No newline at end of file |
index : verismith | ||
Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog. |
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-rw-r--r-- | .gitignore | 3 |
@@ -5,4 +5,5 @@ TAGS .stack-work .shelly equiv* -output*
\ No newline at end of file +output* +failed
\ No newline at end of file |