diff options
| -rw-r--r-- | data/cells_xilinx_7.v | 52 | ||||
| -rw-r--r-- | src/VeriFuzz/Sim/Template.hs | 1 |
2 files changed, 53 insertions, 0 deletions
diff --git a/data/cells_xilinx_7.v b/data/cells_xilinx_7.v index 97ecac7..cfd7578 100644 --- a/data/cells_xilinx_7.v +++ b/data/cells_xilinx_7.v @@ -210,3 +210,55 @@ module FDSE (Q, C, CE, D, S); else if (CE) q_out <= D_in; endmodule + +module LD (Q, D, G); + + parameter INIT = 1'b0; + + output Q; + wire Q; + + input D, G; + + reg q_out; + + initial q_out = INIT; + + assign Q = q_out; + + always @(D or G) + if (G) + q_out <= D; + + specify + if (G) + (D +=> Q) = (100, 100); + (posedge G => (Q +: D)) = (100, 100); + endspecify + +endmodule + +module FD (Q, C, D); + + parameter INIT = 1'b0; + + output Q; + + input C, D; + + wire Q; + reg q_out; + tri0 GSR = glbl.GSR; + + initial q_out = INIT; + + always @(posedge C) + q_out <= D; + + assign Q = q_out; + + specify + (posedge C => (Q +: D)) = (100, 100); + endspecify + +endmodule diff --git a/src/VeriFuzz/Sim/Template.hs b/src/VeriFuzz/Sim/Template.hs index 93f24a3..771646d 100644 --- a/src/VeriFuzz/Sim/Template.hs +++ b/src/VeriFuzz/Sim/Template.hs @@ -90,6 +90,7 @@ write_verilog -force #{outf} -- brittany-disable-next-binding sbyConfig :: (Synthesiser a, Synthesiser b) => FilePath -> a -> Maybe b -> SourceInfo -> Text sbyConfig bd sim1 sim2 (SourceInfo top src) = [st|[options] +multiclock on mode prove [engines] |