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| -rw-r--r-- | examples/simple.v (renamed from test/simple.v) | 0 |
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diff --git a/test/simple.v b/examples/simple.v index 5198d3d..5198d3d 100644 --- a/test/simple.v +++ b/examples/simple.v |
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index : verismith | |
| Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog. |
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