aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat
-rw-r--r--src/Test/VeriFuzz/Graph/ASTGen.hs12
-rw-r--r--src/Test/VeriFuzz/Graph/CodeGen.hs6
-rw-r--r--src/Test/VeriFuzz/Verilog.hs2
-rw-r--r--src/Test/VeriFuzz/Verilog/AST.hs326
-rw-r--r--src/Test/VeriFuzz/Verilog/CodeGen.hs95
-rw-r--r--src/Test/VeriFuzz/Verilog/Helpers.hs18
-rw-r--r--src/Test/VeriFuzz/Verilog/Mutate.hs16
-rw-r--r--tests/Unit.hs40
-rw-r--r--verifuzz.cabal1
9 files changed, 171 insertions, 345 deletions
diff --git a/src/Test/VeriFuzz/Graph/ASTGen.hs b/src/Test/VeriFuzz/Graph/ASTGen.hs
index 3c000ea..2a82592 100644
--- a/src/Test/VeriFuzz/Graph/ASTGen.hs
+++ b/src/Test/VeriFuzz/Graph/ASTGen.hs
@@ -44,16 +44,16 @@ genPortsAST :: (Circuit -> [Node]) -> Circuit -> [Port]
genPortsAST f c =
(port . frNode <$> f c)
where
- port = Port (PortNet Wire) 1
+ port = Port Wire 1
-- | Generates the nested expression AST, so that it can then generate the
-- assignment expressions.
-genAssignExpr :: Gate -> [Node] -> Maybe Expression
+genAssignExpr :: Gate -> [Node] -> Maybe Expr
genAssignExpr g [] = Nothing
-genAssignExpr g (n:[]) = Just . PrimExpr . PrimId $ frNode n
-genAssignExpr g (n:ns) = OpExpr wire op <$> genAssignExpr g ns
+genAssignExpr g (n:[]) = Just . Id $ frNode n
+genAssignExpr g (n:ns) = BinOp wire op <$> genAssignExpr g ns
where
- wire = PrimExpr . PrimId $ frNode n
+ wire = Id $ frNode n
op = fromGate g
-- | Generate the continuous assignment AST for a particular node. If it does
@@ -77,7 +77,7 @@ genModuleDeclAST c = ModDecl id output ports items
where
id = Identifier "gen_module"
ports = genPortsAST inputsC c
- output = [Port (PortNet Wire) 1 "y"]
+ output = [Port Wire 1 "y"]
items = genAssignAST c
generateAST :: Circuit -> VerilogSrc
diff --git a/src/Test/VeriFuzz/Graph/CodeGen.hs b/src/Test/VeriFuzz/Graph/CodeGen.hs
index 64abb0a..eaa109e 100644
--- a/src/Test/VeriFuzz/Graph/CodeGen.hs
+++ b/src/Test/VeriFuzz/Graph/CodeGen.hs
@@ -35,8 +35,8 @@ statList g n = toStr <$> safe tail n
lastEl :: [Node] -> Maybe Text
lastEl n = fromNode <$> safe head n
-toStatement :: (Graph gr) => gr Gate e -> LNode Gate -> Text
-toStatement graph (n, g) =
+toStmnt :: (Graph gr) => gr Gate e -> LNode Gate -> Text
+toStmnt graph (n, g) =
fromMaybe empty $ Just " assign " <> Just (fromNode n)
<> Just " = " <> statList g nodeL <> lastEl nodeL <> Just ";\n"
where
@@ -48,7 +48,7 @@ generate graph =
<> fromList (imap " input wire " ",\n" inp)
<> sep ",\n" (imap " output wire " "" out)
<> ");\n"
- <> fromList (toStatement graph <$> labNodes graph)
+ <> fromList (toStmnt graph <$> labNodes graph)
<> "endmodule\n\nmodule main;\n initial\n begin\n "
<> "$display(\"Hello, world\");\n $finish;\n "
<> "end\nendmodule"
diff --git a/src/Test/VeriFuzz/Verilog.hs b/src/Test/VeriFuzz/Verilog.hs
index 072dc75..d88f885 100644
--- a/src/Test/VeriFuzz/Verilog.hs
+++ b/src/Test/VeriFuzz/Verilog.hs
@@ -18,8 +18,10 @@ module Test.VeriFuzz.Verilog
-- * Verilog mutations
, module Test.VeriFuzz.Verilog.Mutate
, module Test.VeriFuzz.Verilog.Helpers
+ , module Test.VeriFuzz.Verilog.Arbitrary
) where
+import Test.VeriFuzz.Verilog.Arbitrary
import Test.VeriFuzz.Verilog.AST
import Test.VeriFuzz.Verilog.CodeGen
import Test.VeriFuzz.Verilog.Helpers
diff --git a/src/Test/VeriFuzz/Verilog/AST.hs b/src/Test/VeriFuzz/Verilog/AST.hs
index 85c3e99..5ae3202 100644
--- a/src/Test/VeriFuzz/Verilog/AST.hs
+++ b/src/Test/VeriFuzz/Verilog/AST.hs
@@ -15,7 +15,6 @@ Defines the types to build a Verilog AST.
module Test.VeriFuzz.Verilog.AST where
import Control.Lens
-import Control.Monad (replicateM)
import qualified Data.Graph.Inductive as G
import Data.String
import Data.Text (Text)
@@ -33,34 +32,26 @@ class Source a where
newtype Identifier = Identifier { _getIdentifier :: Text }
deriving (Show, Eq, Ord)
--- | A number in Verilog which contains a size and a value.
-data Number = Number { _numSize :: Int
- , _numVal :: Int
- } deriving (Show, Eq, Ord)
+instance IsString Identifier where
+ fromString = Identifier . T.pack
+
+instance Semigroup Identifier where
+ (Identifier a) <> (Identifier b) = Identifier (a <> b)
+
+instance Monoid Identifier where
+ mempty = Identifier mempty
newtype Delay = Delay { _delay :: Int }
deriving (Show, Eq, Ord)
data Event = EId Identifier
- | EExpr Expression
+ | EExpr Expr
| EAll
deriving (Show, Eq, Ord)
-data Net = Wire
- | Tri
- | Tri1
- | Supply0
- | Wand
- | TriAnd
- | Tri0
- | Supply1
- | Wor
- | Trior
- deriving (Show, Eq, Ord)
-
data RegLVal = RegId Identifier
| RegExpr { _regExprId :: Identifier
- , _regExpr :: Expression
+ , _regExpr :: Expr
}
| RegSize { _regSizeId :: Identifier
, _regSizeMSB :: ConstExpr
@@ -109,38 +100,61 @@ data UnaryOperator = UnPlus -- ^ @+@
| UnNxorInv -- ^ @^~@
deriving (Show, Eq, Ord)
--- | A primary expression which can either be a number or an identifier.
-data Primary = PrimNum Number -- ^ Number in primary expression.
- | PrimId Identifier -- ^ Identifier in primary expression.
- deriving (Show, Eq, Ord)
-
-- | Verilog expression, which can either be a primary expression, unary
-- expression, binary operator expression or a conditional expression.
-data Expression = PrimExpr Primary
- | UnPrimExpr { _exprUnOp :: UnaryOperator
- , _exprPrim :: Primary
- }
- | OpExpr { _exprLhs :: Expression
- , _exprBinOp :: BinaryOperator
- , _exprRhs :: Expression
- }
- | CondExpr { _exprCond :: Expression
- , _exprTrue :: Expression
- , _exprFalse :: Expression
- }
- | ExprStr Text
- deriving (Show, Eq, Ord)
+data Expr = Number { _numSize :: Int
+ , _numVal :: Int
+ }
+ | Id { _exprId :: Identifier }
+ | Concat { _concatExpr :: [Expr] }
+ | UnOp { _exprUnOp :: UnaryOperator
+ , _exprPrim :: Expr
+ }
+ | BinOp { _exprLhs :: Expr
+ , _exprBinOp :: BinaryOperator
+ , _exprRhs :: Expr
+ }
+ | Cond { _exprCond :: Expr
+ , _exprTrue :: Expr
+ , _exprFalse :: Expr
+ }
+ | Str { _exprStr :: Text }
+ deriving (Show, Eq, Ord)
+
+instance Num Expr where
+ a + b = BinOp a BinPlus b
+ a - b = BinOp a BinMinus b
+ a * b = BinOp a BinTimes b
+ negate = UnOp UnMinus
+ abs = undefined
+ signum = undefined
+ fromInteger = Number 32 . fromInteger
+
+instance Semigroup Expr where
+ a <> b = mconcat [a, b]
+
+instance Monoid Expr where
+ mempty = 0
+ mconcat = Concat
newtype ConstExpr = ConstExpr { _constNum :: Int }
deriving (Show, Eq, Ord)
+instance Num ConstExpr where
+ ConstExpr a + ConstExpr b = ConstExpr $ a + b
+ ConstExpr a * ConstExpr b = ConstExpr $ a * b
+ ConstExpr a - ConstExpr b = ConstExpr $ a - b
+ abs (ConstExpr a) = ConstExpr $ abs a
+ signum (ConstExpr a) = ConstExpr $ signum a
+ fromInteger = ConstExpr . fromInteger
+
-- | Different port direction that are supported in Verilog.
data PortDir = PortIn -- ^ Input direction for port (@input@).
| PortOut -- ^ Output direction for port (@output@).
| PortInOut -- ^ Inout direction for port (@inout@).
deriving (Show, Eq, Ord)
-data PortType = PortNet Net
+data PortType = Wire
| Reg { _regSigned :: Bool }
deriving (Show, Eq, Ord)
@@ -150,35 +164,43 @@ data Port = Port { _portType :: PortType
, _portName :: Identifier
} deriving (Show, Eq, Ord)
-newtype ModConn = ModConn { _modConn :: Expression }
+newtype ModConn = ModConn { _modConn :: Expr }
deriving (Show, Eq, Ord)
data Assign = Assign { _assignReg :: RegLVal
, _assignDelay :: Maybe Delay
- , _assignExpr :: Expression
+ , _assignExpr :: Expr
} deriving (Show, Eq, Ord)
data ContAssign = ContAssign { _contAssignNetLVal :: Identifier
- , _contAssignExpr :: Expression
+ , _contAssignExpr :: Expr
} deriving (Show, Eq, Ord)
--- | Statements in Verilog.
-data Statement = TimeCtrl { _statDelay :: Delay
- , _statDStat :: Maybe Statement
+-- | Stmnts in Verilog.
+data Stmnt = TimeCtrl { _statDelay :: Delay
+ , _statDStat :: Maybe Stmnt
} -- ^ Time control (@#NUM@)
| EventCtrl { _statEvent :: Event
- , _statEStat :: Maybe Statement
+ , _statEStat :: Maybe Stmnt
}
- | SeqBlock { _statements :: [Statement] } -- ^ Sequential block (@begin ... end@)
+ | SeqBlock { _statements :: [Stmnt] } -- ^ Sequential block (@begin ... end@)
| BlockAssign Assign -- ^ blocking assignment (@=@)
| NonBlockAssign Assign -- ^ Non blocking assignment (@<=@)
- | StatCA ContAssign -- ^ Statement continuous assignment. May not be correct.
+ | StatCA ContAssign -- ^ Stmnt continuous assignment. May not be correct.
| TaskEnable Task
| SysTaskEnable Task
+ | EmptyStat
deriving (Show, Eq, Ord)
+instance Semigroup Stmnt where
+ a <> b = mconcat [a, b]
+
+instance Monoid Stmnt where
+ mempty = EmptyStat
+ mconcat = SeqBlock
+
data Task = Task { _taskName :: Identifier
- , _taskExpr :: [Expression]
+ , _taskExpr :: [Expr]
} deriving (Show, Eq, Ord)
-- | Module item which is the body of the module expression.
@@ -187,8 +209,8 @@ data ModItem = ModCA ContAssign
, _modInstName :: Identifier
, _modInstConns :: [ModConn]
}
- | Initial Statement
- | Always Statement
+ | Initial Stmnt
+ | Always Stmnt
| Decl { declDir :: Maybe PortDir
, declPort :: Port
}
@@ -209,200 +231,25 @@ newtype Description = Description { _getDescription :: ModDecl }
newtype VerilogSrc = VerilogSrc { _getVerilogSrc :: [Description] }
deriving (Show, Eq, Ord)
--- Generate Arbitrary instances for the AST
-
-positiveArb :: (QC.Arbitrary a, Ord a, Num a) => QC.Gen a
-positiveArb = QC.suchThat QC.arbitrary (>0)
-
-expr :: Int -> QC.Gen Expression
-expr 0 = QC.oneof
- [ PrimExpr <$> QC.arbitrary
- , UnPrimExpr <$> QC.arbitrary <*> QC.arbitrary
- -- , ExprStr <$> QC.arbitrary
- ]
-expr n
- | n > 0 = QC.oneof
- [ PrimExpr <$> QC.arbitrary
- , UnPrimExpr <$> QC.arbitrary <*> QC.arbitrary
- -- , ExprStr <$> QC.arbitrary
- , OpExpr <$> subexpr 2 <*> QC.arbitrary <*> subexpr 2
- , CondExpr <$> subexpr 3 <*> subexpr 3 <*> subexpr 3
- ]
- | otherwise = expr 0
- where
- subexpr y = expr (n `div` y)
-
-statement :: Int -> QC.Gen Statement
-statement 0 = QC.oneof
- [ BlockAssign <$> QC.arbitrary
- , NonBlockAssign <$> QC.arbitrary
- -- , StatCA <$> QC.arbitrary
- , TaskEnable <$> QC.arbitrary
- , SysTaskEnable <$> QC.arbitrary
- ]
-statement n
- | n > 0 = QC.oneof
- [ TimeCtrl <$> QC.arbitrary <*> (Just <$> substat 2)
- , SeqBlock <$> QC.listOf1 (substat 4)
- , BlockAssign <$> QC.arbitrary
- , NonBlockAssign <$> QC.arbitrary
- -- , StatCA <$> QC.arbitrary
- , TaskEnable <$> QC.arbitrary
- , SysTaskEnable <$> QC.arbitrary
- ]
- | otherwise = statement 0
- where
- substat y = statement (n `div` y)
-
-modPortGen :: QC.Gen Port
-modPortGen = QC.oneof
- [ Port (PortNet Wire) <$> positiveArb <*> QC.arbitrary
- , Port <$> (Reg <$> QC.arbitrary) <*> positiveArb <*> QC.arbitrary
- ]
-
-instance QC.Arbitrary Text where
- arbitrary = T.pack <$> QC.arbitrary
-
-instance QC.Arbitrary Identifier where
- arbitrary = do
- l <- QC.choose (2, 10)
- Identifier . T.pack <$> replicateM l (QC.elements ['a'..'z'])
-
-instance QC.Arbitrary Number where
- arbitrary = Number <$> positiveArb <*> QC.arbitrary
-
-instance QC.Arbitrary Net where
- arbitrary = pure Wire
-
-instance QC.Arbitrary BinaryOperator where
- arbitrary = QC.elements
- [ BinPlus
- , BinMinus
- , BinTimes
- , BinDiv
- , BinMod
- , BinEq
- , BinNEq
- , BinCEq
- , BinCNEq
- , BinLAnd
- , BinLOr
- , BinLT
- , BinLEq
- , BinGT
- , BinGEq
- , BinAnd
- , BinOr
- , BinXor
- , BinXNor
- , BinXNorInv
- , BinPower
- , BinLSL
- , BinLSR
- , BinASL
- , BinASR
- ]
-
-instance QC.Arbitrary UnaryOperator where
- arbitrary = QC.elements
- [ UnPlus
- , UnMinus
- , UnNot
- , UnAnd
- , UnNand
- , UnOr
- , UnNor
- , UnXor
- , UnNxor
- , UnNxorInv
- ]
-
-instance QC.Arbitrary Primary where
- arbitrary = PrimNum <$> QC.arbitrary
-
-instance QC.Arbitrary PortDir where
- arbitrary = QC.elements [PortIn, PortOut, PortInOut]
-
-instance QC.Arbitrary PortType where
- arbitrary = QC.oneof [PortNet <$> QC.arbitrary, Reg <$> QC.arbitrary]
-
-instance QC.Arbitrary Port where
- arbitrary = Port <$> QC.arbitrary <*> positiveArb <*> QC.arbitrary
-
-instance QC.Arbitrary Delay where
- arbitrary = Delay <$> positiveArb
-
-instance QC.Arbitrary Event where
- arbitrary = EId <$> QC.arbitrary
-
-instance QC.Arbitrary ModConn where
- arbitrary = ModConn <$> QC.arbitrary
-
-instance QC.Arbitrary ConstExpr where
- arbitrary = ConstExpr <$> positiveArb
-
-instance QC.Arbitrary RegLVal where
- arbitrary = QC.oneof [ RegId <$> QC.arbitrary
- , RegExpr <$> QC.arbitrary <*> QC.arbitrary
- , RegSize <$> QC.arbitrary <*> QC.arbitrary <*> QC.arbitrary
- ]
-
-instance QC.Arbitrary Assign where
- arbitrary = Assign <$> QC.arbitrary <*> QC.arbitrary <*> QC.arbitrary
-
-instance QC.Arbitrary Expression where
- arbitrary = QC.sized expr
-
-instance QC.Arbitrary Statement where
- arbitrary = QC.sized statement
-
-instance QC.Arbitrary ContAssign where
- arbitrary = ContAssign <$> QC.arbitrary <*> QC.arbitrary
-
-instance QC.Arbitrary Task where
- arbitrary = Task <$> QC.arbitrary <*> QC.arbitrary
-
-instance QC.Arbitrary ModItem where
- arbitrary = QC.oneof [ ModCA <$> QC.arbitrary
- , ModInst <$> QC.arbitrary <*> QC.arbitrary <*> QC.arbitrary
- , Initial <$> QC.arbitrary
- , Always <$> (EventCtrl <$> QC.arbitrary <*> QC.arbitrary)
- , Decl <$> pure Nothing <*> QC.arbitrary
- ]
-
-instance QC.Arbitrary ModDecl where
- arbitrary = ModDecl <$> QC.arbitrary <*> QC.arbitrary
- <*> QC.listOf1 modPortGen <*> QC.arbitrary
-
-instance QC.Arbitrary Description where
- arbitrary = Description <$> QC.arbitrary
-
-instance QC.Arbitrary VerilogSrc where
- arbitrary = VerilogSrc <$> QC.arbitrary
-
--- Other Instances
+instance Semigroup VerilogSrc where
+ VerilogSrc a <> VerilogSrc b = VerilogSrc $ a ++ b
-instance IsString Identifier where
- fromString = Identifier . T.pack
-
-instance Semigroup Identifier where
- (Identifier a) <> (Identifier b) = Identifier (a <> b)
-
-instance Monoid Identifier where
- mempty = Identifier mempty
+instance Monoid VerilogSrc where
+ mempty = VerilogSrc []
-- Traversal Instance
-traverseExpr :: Traversal' Expression Expression
-traverseExpr _ (PrimExpr e) = pure (PrimExpr e)
-traverseExpr _ (UnPrimExpr un e) = pure (UnPrimExpr un e)
-traverseExpr f (OpExpr l op r) = OpExpr <$> f l <*> pure op <*> f r
-traverseExpr f (CondExpr c l r) = CondExpr <$> f c <*> f l <*> f r
+traverseExpr :: Traversal' Expr Expr
+traverseExpr _ (Number s v) = pure $ Number s v
+traverseExpr _ (Id id) = pure $ Id id
+traverseExpr f (Concat e) = Concat <$> (sequenceA $ f <$> e)
+traverseExpr f (UnOp un e) = UnOp un <$> f e
+traverseExpr f (BinOp l op r) = BinOp <$> f l <*> pure op <*> f r
+traverseExpr f (Cond c l r) = Cond <$> f c <*> f l <*> f r
-- Create all the necessary lenses
makeLenses ''Identifier
-makeLenses ''Number
makeLenses ''VerilogSrc
makeLenses ''Description
makeLenses ''ModDecl
@@ -411,13 +258,12 @@ makeLenses ''Port
makeLenses ''PortDir
makeLenses ''BinaryOperator
makeLenses ''UnaryOperator
-makeLenses ''Primary
-makeLenses ''Expression
+makeLenses ''Expr
makeLenses ''ContAssign
makeLenses ''PortType
-- Make all the necessary prisms
-makePrisms ''Expression
+makePrisms ''Expr
makePrisms ''ModItem
makePrisms ''ModConn
diff --git a/src/Test/VeriFuzz/Verilog/CodeGen.hs b/src/Test/VeriFuzz/Verilog/CodeGen.hs
index 9902d32..9e99f70 100644
--- a/src/Test/VeriFuzz/Verilog/CodeGen.hs
+++ b/src/Test/VeriFuzz/Verilog/CodeGen.hs
@@ -21,11 +21,14 @@ import qualified Data.Text.IO as T
import Test.VeriFuzz.Internal.Shared
import Test.VeriFuzz.Verilog.AST
+comma :: [Text] -> Text
+comma = T.intercalate ", "
+
showT :: (Show a) => a -> Text
showT = T.pack . show
-defMap :: Maybe Statement -> Text
-defMap stat = fromMaybe ";\n" $ genStatement <$> stat
+defMap :: Maybe Stmnt -> Text
+defMap stat = fromMaybe ";\n" $ genStmnt <$> stat
-- | Convert the 'VerilogSrc' type to 'Text' so that it can be rendered.
genVerilogSrc :: VerilogSrc -> Text
@@ -47,7 +50,7 @@ genModuleDecl mod =
where
ports
| noIn && noOut = ""
- | otherwise = "(" <> (sep ", " $ genModPort <$> outIn) <> ")"
+ | otherwise = "(" <> (comma $ genModPort <$> outIn) <> ")"
modItems = fromList $ genModuleItem <$> mod ^. moduleItems
noOut = null $ mod ^. modOutPorts
noIn = null $ mod ^. modInPorts
@@ -77,41 +80,35 @@ genPortDir PortInOut = "inout"
genModuleItem :: ModItem -> Text
genModuleItem (ModCA ca) = genContAssign ca
genModuleItem (ModInst (Identifier id) (Identifier name) conn) =
- id <> " " <> name <> "(" <> sep ", " (genExpr . _modConn <$> conn) <> ")" <> ";\n"
-genModuleItem (Initial stat) = "initial " <> genStatement stat
-genModuleItem (Always stat) = "always " <> genStatement stat
+ id <> " " <> name <> "(" <> comma (genExpr . _modConn <$> conn) <> ")" <> ";\n"
+genModuleItem (Initial stat) = "initial " <> genStmnt stat
+genModuleItem (Always stat) = "always " <> genStmnt stat
genModuleItem (Decl dir port) =
(fromMaybe "" $ ((<>" ") . genPortDir) <$> dir) <> genPort port <> ";\n"
-- | Generate continuous assignment
genContAssign :: ContAssign -> Text
genContAssign (ContAssign val e) =
- " assign " <> name <> " = " <> expr <> ";\n"
+ "assign " <> name <> " = " <> expr <> ";\n"
where
name = val ^. getIdentifier
expr = genExpr $ e
--- | Generate 'Expression' to 'Text'.
-genExpr :: Expression -> Text
-genExpr (OpExpr exprRhs bin exprLhs) =
+-- | Generate 'Expr' to 'Text'.
+genExpr :: Expr -> Text
+genExpr (BinOp exprRhs bin exprLhs) =
"(" <> genExpr exprRhs <> genBinaryOperator bin <> genExpr exprLhs <> ")"
-genExpr (PrimExpr prim) = genPrimary prim
-genExpr (UnPrimExpr u e) =
- "(" <> genUnaryOperator u <> genPrimary e <> ")"
-genExpr (CondExpr l t f) =
- "(" <> genExpr l <> " ? " <> genExpr t <> " : " <> genExpr f <> ")"
-genExpr (ExprStr t) = "\"" <> t <> "\""
-
--- | Generate a 'PrimaryExpression' to 'Text'.
-genPrimary :: Primary -> Text
-genPrimary (PrimNum num) =
- "(" <> neg <> sh (num ^. numSize) <> "'d" <> (sh . abs) n <> ")"
+genExpr (Number s n) =
+ "(" <> sh (s * signum n) <> "'d" <> (sh . abs) n <> ")"
where
sh = T.pack . show
- abs x = if x <= 0 then -x else x
- n = num ^. numVal
- neg = if n <= 0 then "-" else ""
-genPrimary (PrimId ident) = ident ^. getIdentifier
+genExpr (Id i) = i ^. getIdentifier
+genExpr (Concat c) = "{" <> comma (genExpr <$> c) <> "}"
+genExpr (UnOp u e) =
+ "(" <> genUnaryOperator u <> genExpr e <> ")"
+genExpr (Cond l t f) =
+ "(" <> genExpr l <> " ? " <> genExpr t <> " : " <> genExpr f <> ")"
+genExpr (Str t) = "\"" <> t <> "\""
-- | Convert 'BinaryOperator' to 'Text'.
genBinaryOperator :: BinaryOperator -> Text
@@ -153,18 +150,6 @@ genUnaryOperator UnXor = "^"
genUnaryOperator UnNxor = "~^"
genUnaryOperator UnNxorInv = "^~"
-genNet :: Net -> Text
-genNet Wire = "wire"
-genNet Tri = "tri"
-genNet Tri1 = "tri1"
-genNet Supply0 = "supply0"
-genNet Wand = "wand"
-genNet TriAnd = "triand"
-genNet Tri0 = "tri0"
-genNet Supply1 = "supply1"
-genNet Wor = "wor"
-genNet Trior = "trior"
-
genEvent :: Event -> Text
genEvent (EId id) = "@(" <> id ^. getIdentifier <> ")"
genEvent (EExpr expr) = "@(" <> genExpr expr <> ")"
@@ -184,7 +169,7 @@ genConstExpr :: ConstExpr -> Text
genConstExpr (ConstExpr num) = showT num
genPortType :: PortType -> Text
-genPortType (PortNet net) = genNet net
+genPortType Wire = "wire"
genPortType (Reg signed)
| signed = "reg signed"
| otherwise = "reg"
@@ -193,21 +178,21 @@ genAssign :: Text -> Assign -> Text
genAssign op (Assign r d e) =
genRegLVal r <> op <> fromMaybe "" (genDelay <$> d) <> genExpr e
-genStatement :: Statement -> Text
-genStatement (TimeCtrl d stat) = genDelay d <> " " <> defMap stat
-genStatement (EventCtrl e stat) = genEvent e <> " " <> defMap stat
-genStatement (SeqBlock s) =
- "begin\n" <> fromList (genStatement <$> s) <> "end\n"
-genStatement (BlockAssign a) = genAssign " = " a <> ";\n"
-genStatement (NonBlockAssign a) = genAssign " <= " a <> ";\n"
-genStatement (StatCA a) = genContAssign a
-genStatement (TaskEnable task) = genTask task <> ";\n"
-genStatement (SysTaskEnable task) = "$" <> genTask task <> ";\n"
+genStmnt :: Stmnt -> Text
+genStmnt (TimeCtrl d stat) = genDelay d <> " " <> defMap stat
+genStmnt (EventCtrl e stat) = genEvent e <> " " <> defMap stat
+genStmnt (SeqBlock s) =
+ "begin\n" <> fromList (genStmnt <$> s) <> "end\n"
+genStmnt (BlockAssign a) = genAssign " = " a <> ";\n"
+genStmnt (NonBlockAssign a) = genAssign " <= " a <> ";\n"
+genStmnt (StatCA a) = genContAssign a
+genStmnt (TaskEnable task) = genTask task <> ";\n"
+genStmnt (SysTaskEnable task) = "$" <> genTask task <> ";\n"
genTask :: Task -> Text
genTask (Task name expr)
| null expr = id
- | otherwise = id <> "(" <> sep ", " (genExpr <$> expr) <> ")"
+ | otherwise = id <> "(" <> comma (genExpr <$> expr) <> ")"
where
id = name ^. getIdentifier
@@ -220,8 +205,8 @@ render = T.putStrLn
instance Source Task where
genSource = genTask
-instance Source Statement where
- genSource = genStatement
+instance Source Stmnt where
+ genSource = genStmnt
instance Source PortType where
genSource = genPortType
@@ -238,16 +223,10 @@ instance Source Delay where
instance Source Event where
genSource = genEvent
-instance Source Net where
- genSource = genNet
-
instance Source UnaryOperator where
genSource = genUnaryOperator
-instance Source Primary where
- genSource = genPrimary
-
-instance Source Expression where
+instance Source Expr where
genSource = genExpr
instance Source ContAssign where
diff --git a/src/Test/VeriFuzz/Verilog/Helpers.hs b/src/Test/VeriFuzz/Verilog/Helpers.hs
index d3bc689..b04aa76 100644
--- a/src/Test/VeriFuzz/Verilog/Helpers.hs
+++ b/src/Test/VeriFuzz/Verilog/Helpers.hs
@@ -21,14 +21,10 @@ regDecl :: Identifier -> ModItem
regDecl = Decl Nothing . Port (Reg False) 1
wireDecl :: Identifier -> ModItem
-wireDecl = Decl Nothing . Port (PortNet Wire) 1
+wireDecl = Decl Nothing . Port Wire 1
-modConn :: Text -> ModConn
-modConn = ModConn . PrimExpr . PrimId . Identifier
-
--- | Create a number expression which will be stored in a primary expression.
-numExpr :: Int -> Int -> Expression
-numExpr = ((PrimExpr . PrimNum) .) . Number
+modConn :: Identifier -> ModConn
+modConn = ModConn . Id
-- | Create an empty module.
emptyMod :: ModDecl
@@ -57,10 +53,10 @@ testBench =
, modConn "b"
]
, Initial $ SeqBlock
- [ BlockAssign . Assign (RegId "a") Nothing . PrimExpr . PrimNum $ Number 1 1
- , BlockAssign . Assign (RegId "b") Nothing . PrimExpr . PrimNum $ Number 1 1
+ [ BlockAssign . Assign (RegId "a") Nothing $ Number 1 1
+ , BlockAssign . Assign (RegId "b") Nothing $ Number 1 1
-- , TimeCtrl (Delay 1) . Just . SysTaskEnable $ Task "display"
- -- [ ExprStr "%d & %d = %d"
+ -- [ Str "%d & %d = %d"
-- , PrimExpr $ PrimId "a"
-- , PrimExpr $ PrimId "b"
-- , PrimExpr $ PrimId "c"
@@ -73,4 +69,4 @@ addTestBench :: VerilogSrc -> VerilogSrc
addTestBench = addDescription $ Description testBench
defaultPort :: Identifier -> Port
-defaultPort = Port (PortNet Wire) 1
+defaultPort = Port Wire 1
diff --git a/src/Test/VeriFuzz/Verilog/Mutate.hs b/src/Test/VeriFuzz/Verilog/Mutate.hs
index 1d58007..9175664 100644
--- a/src/Test/VeriFuzz/Verilog/Mutate.hs
+++ b/src/Test/VeriFuzz/Verilog/Mutate.hs
@@ -28,7 +28,7 @@ inPort id mod = inInput
-- | Find the last assignment of a specific wire/reg to an expression, and
-- returns that expression.
-findAssign :: Identifier -> [ModItem] -> Maybe Expression
+findAssign :: Identifier -> [ModItem] -> Maybe Expr
findAssign id items =
safe last . catMaybes $ isAssign <$> items
where
@@ -40,14 +40,14 @@ findAssign id items =
-- | Transforms an expression by replacing an Identifier with an
-- expression. This is used inside 'transformOf' and 'traverseExpr' to replace
-- the 'Identifier' recursively.
-idTrans :: Identifier -> Expression -> Expression -> Expression
-idTrans i expr (PrimExpr (PrimId id))
+idTrans :: Identifier -> Expr -> Expr -> Expr
+idTrans i expr (Id id)
| id == i = expr
- | otherwise = (PrimExpr (PrimId id))
+ | otherwise = (Id id)
idTrans _ _ e = e
-- | Replaces the identifier recursively in an expression.
-replace :: Identifier -> Expression -> Expression -> Expression
+replace :: Identifier -> Expr -> Expr -> Expr
replace = (transformOf traverseExpr .) . idTrans
-- | Nest expressions for a specific 'Identifier'. If the 'Identifier' is not found,
@@ -64,7 +64,7 @@ nestId id mod
| otherwise = mod
where
get = moduleItems . traverse . _ModCA . contAssignExpr
- def = PrimExpr $ PrimId id
+ def = Id id
-- | Replaces an identifier by a expression in all the module declaration.
nestSource :: Identifier -> VerilogSrc -> VerilogSrc
@@ -77,7 +77,7 @@ nestUpTo i src =
foldl (flip nestSource) src $ Identifier . fromNode <$> [1..i]
-- $setup
--- >>> let mod = (ModDecl (Identifier "m") [Port (PortNet Wire) 5 (Identifier "y")] [Port (PortNet Wire) 5 "x"] [])
+-- >>> let mod = (ModDecl (Identifier "m") [Port Wire 5 (Identifier "y")] [Port Wire 5 "x"] [])
-- >>> let main = (ModDecl "main" [] [] [])
-- | Add a Module Instantiation using 'ModInst' from the first module passed to
@@ -99,7 +99,7 @@ instantiateMod mod main =
regIn = Decl Nothing <$> (mod ^. modInPorts & traverse . portType .~ Reg False)
inst = ModInst (mod ^. moduleId) (mod ^. moduleId <> (Identifier . showT $ count+1)) conns
count = length . filter (==mod ^. moduleId) $ main ^.. moduleItems . traverse . modInstId
- conns = ModConn . PrimExpr . PrimId <$>
+ conns = ModConn . Id <$>
(mod ^.. modOutPorts . traverse . portName) ++ (mod ^.. modInPorts . traverse . portName)
-- | Initialise all the inputs and outputs to a module.
diff --git a/tests/Unit.hs b/tests/Unit.hs
index de4fa16..13b9027 100644
--- a/tests/Unit.hs
+++ b/tests/Unit.hs
@@ -14,27 +14,29 @@ unitTests = testGroup "Unit tests"
(transformOf traverseExpr trans transformTestData)
]
-primExpr :: Text -> Expression
-primExpr = PrimExpr . PrimId . Identifier
+transformTestData :: Expr
+transformTestData = BinOp (BinOp (BinOp (Id "id1") BinAnd (Id "id2")) BinAnd
+ (BinOp (Id "id1") BinAnd (Id "id2"))) BinAnd
+ (BinOp (BinOp (BinOp (Id "id1") BinAnd (Id "id2")) BinAnd
+ (BinOp (Id "id1") BinAnd (BinOp (BinOp (Id "id1") BinAnd (Id "id2")) BinAnd
+ (BinOp (Id "id1") BinAnd (Id "id2"))))) BinOr
+ (Concat [Concat [ Concat [Id "id1", Id "id2", Id "id2"], Id "id2", Id "id2"
+ , Concat [Id "id2", Id "id2", Concat [Id "id1", Id "id2"]]
+ , Id "id2"], Id "id1", Id "id2"]))
-transformTestData :: Expression
-transformTestData = OpExpr (OpExpr (OpExpr (primExpr "id1") BinAnd (primExpr "id2")) BinAnd
- (OpExpr (primExpr "id1") BinAnd (primExpr "id2"))) BinAnd
- (OpExpr (OpExpr (primExpr "id1") BinAnd (primExpr "id2")) BinAnd
- (OpExpr (primExpr "id1") BinAnd (OpExpr (OpExpr (primExpr "id1") BinAnd (primExpr "id2")) BinAnd
- (OpExpr (primExpr "id1") BinAnd (primExpr "id2")))))
-
-transformExpectedResult :: Expression
-transformExpectedResult = OpExpr (OpExpr (OpExpr (primExpr "id1") BinAnd (primExpr "Replaced")) BinAnd
- (OpExpr (primExpr "id1") BinAnd (primExpr "Replaced"))) BinAnd
- (OpExpr (OpExpr (primExpr "id1") BinAnd (primExpr "Replaced")) BinAnd
- (OpExpr (primExpr "id1") BinAnd (OpExpr (OpExpr (primExpr "id1") BinAnd
- (primExpr "Replaced")) BinAnd
- (OpExpr (primExpr "id1") BinAnd (primExpr "Replaced")))))
+transformExpectedResult :: Expr
+transformExpectedResult = BinOp (BinOp (BinOp (Id "id1") BinAnd (Id "Replaced")) BinAnd
+ (BinOp (Id "id1") BinAnd (Id "Replaced"))) BinAnd
+ (BinOp (BinOp (BinOp (Id "id1") BinAnd (Id "Replaced")) BinAnd
+ (BinOp (Id "id1") BinAnd (BinOp (BinOp (Id "id1") BinAnd (Id "Replaced")) BinAnd
+ (BinOp (Id "id1") BinAnd (Id "Replaced"))))) BinOr
+ (Concat [Concat [ Concat [Id "id1", Id "Replaced", Id "Replaced"], Id "Replaced", Id "Replaced"
+ , Concat [Id "Replaced", Id "Replaced", Concat [Id "id1", Id "Replaced"]]
+ , Id "Replaced"], Id "id1", Id "Replaced"]))
trans e =
case e of
- PrimExpr (PrimId id) -> if id == Identifier "id2" then
- PrimExpr . PrimId $ Identifier "Replaced"
- else PrimExpr (PrimId id)
+ Id id -> if id == Identifier "id2" then
+ Id $ Identifier "Replaced"
+ else Id id
_ -> e
diff --git a/verifuzz.cabal b/verifuzz.cabal
index fcc4965..6f878ff 100644
--- a/verifuzz.cabal
+++ b/verifuzz.cabal
@@ -31,6 +31,7 @@ library
, Test.VeriFuzz.Simulator.Yosys
, Test.VeriFuzz.Verilog
, Test.VeriFuzz.Verilog.AST
+ , Test.VeriFuzz.Verilog.Arbitrary
, Test.VeriFuzz.Verilog.CodeGen
, Test.VeriFuzz.Verilog.Helpers
, Test.VeriFuzz.Verilog.Mutate
generated by cgit (git 2.34.1) at 2024-07-03 08:39:40 +0000