diff options
| -rw-r--r-- | app/Main.hs | 4 | ||||
| -rw-r--r-- | src/VeriFuzz.hs | 28 | ||||
| -rw-r--r-- | src/VeriFuzz/Simulator.hs | 20 | ||||
| -rw-r--r-- | src/VeriFuzz/Verilog.hs | 24 | ||||
| -rw-r--r-- | src/VeriFuzz/Verilog/Arbitrary.hs | 224 | ||||
| -rw-r--r-- | test/Property.hs | 4 | ||||
| -rw-r--r-- | test/Test.hs | 2 | ||||
| -rw-r--r-- | test/Unit.hs | 2 | ||||
| -rw-r--r-- | verifuzz.cabal | 38 |
9 files changed, 116 insertions, 230 deletions
diff --git a/app/Main.hs b/app/Main.hs index 50ea261..2e90b37 100644 --- a/app/Main.hs +++ b/app/Main.hs @@ -14,8 +14,8 @@ import Numeric (showHex) import Numeric.Natural (Natural) import Shelly import qualified Test.QuickCheck as QC -import Test.VeriFuzz -import qualified Test.VeriFuzz.Graph.RandomAlt as V +import VeriFuzz +import qualified VeriFuzz.Graph.RandomAlt as V genRand :: C.CtrDRBG -> Int -> [ByteString] -> [ByteString] genRand gen n bytes diff --git a/src/VeriFuzz.hs b/src/VeriFuzz.hs index a3204b3..4f34ec9 100644 --- a/src/VeriFuzz.hs +++ b/src/VeriFuzz.hs @@ -1,5 +1,5 @@ {-| -Module : Test.VeriFuzz +Module : VeriFuzz Description : VeriFuzz Copyright : (c) 2018-2019, Yann Herklotz Grave License : BSD-3 @@ -8,23 +8,23 @@ Stability : experimental Portability : POSIX -} -module Test.VeriFuzz +module VeriFuzz ( -- * Definitions - module Test.VeriFuzz.Circuit + module VeriFuzz.Circuit -- * Verilog AST Data Types - , module Test.VeriFuzz.Verilog + , module VeriFuzz.Verilog -- * Graphs - , module Test.VeriFuzz.Graph.ASTGen - , module Test.VeriFuzz.Graph.CodeGen - , module Test.VeriFuzz.Graph.Random + , module VeriFuzz.Graph.ASTGen + , module VeriFuzz.Graph.CodeGen + , module VeriFuzz.Graph.Random -- * Simulator - , module Test.VeriFuzz.Simulator + , module VeriFuzz.Simulator ) where -import Test.VeriFuzz.Circuit -import Test.VeriFuzz.Graph.ASTGen -import Test.VeriFuzz.Graph.CodeGen -import Test.VeriFuzz.Graph.Random -import Test.VeriFuzz.Simulator -import Test.VeriFuzz.Verilog +import VeriFuzz.Circuit +import VeriFuzz.Graph.ASTGen +import VeriFuzz.Graph.CodeGen +import VeriFuzz.Graph.Random +import VeriFuzz.Simulator +import VeriFuzz.Verilog diff --git a/src/VeriFuzz/Simulator.hs b/src/VeriFuzz/Simulator.hs index cadaffd..0a2cf44 100644 --- a/src/VeriFuzz/Simulator.hs +++ b/src/VeriFuzz/Simulator.hs @@ -1,5 +1,5 @@ {-| -Module : Test.VeriFuzz.Simulator +Module : VeriFuzz.Simulator Description : Simulator module. Copyright : (c) 2018-2019, Yann Herklotz Grave License : BSD-3 @@ -10,14 +10,14 @@ Portability : POSIX Simulator module. -} -module Test.VeriFuzz.Simulator - ( module Test.VeriFuzz.Simulator.General - , module Test.VeriFuzz.Simulator.Yosys - , module Test.VeriFuzz.Simulator.Xst - , module Test.VeriFuzz.Simulator.Icarus +module VeriFuzz.Simulator + ( module VeriFuzz.Simulator.General + , module VeriFuzz.Simulator.Yosys + , module VeriFuzz.Simulator.Xst + , module VeriFuzz.Simulator.Icarus ) where -import Test.VeriFuzz.Simulator.General -import Test.VeriFuzz.Simulator.Icarus -import Test.VeriFuzz.Simulator.Xst -import Test.VeriFuzz.Simulator.Yosys +import VeriFuzz.Simulator.General +import VeriFuzz.Simulator.Icarus +import VeriFuzz.Simulator.Xst +import VeriFuzz.Simulator.Yosys diff --git a/src/VeriFuzz/Verilog.hs b/src/VeriFuzz/Verilog.hs index d88f885..baed3c5 100644 --- a/src/VeriFuzz/Verilog.hs +++ b/src/VeriFuzz/Verilog.hs @@ -1,5 +1,5 @@ {-| -Module : Test.VeriFuzz.Verilog +Module : VeriFuzz.Verilog Description : The main verilog module with the syntax and code generation. Copyright : (c) 2018-2019, Yann Herklotz Grave License : BSD-3 @@ -10,19 +10,19 @@ Portability : POSIX The main verilog module with the syntax and code generation. -} -module Test.VeriFuzz.Verilog +module VeriFuzz.Verilog ( -- * AST - module Test.VeriFuzz.Verilog.AST + module VeriFuzz.Verilog.AST -- * Code Generation - , module Test.VeriFuzz.Verilog.CodeGen + , module VeriFuzz.Verilog.CodeGen -- * Verilog mutations - , module Test.VeriFuzz.Verilog.Mutate - , module Test.VeriFuzz.Verilog.Helpers - , module Test.VeriFuzz.Verilog.Arbitrary + , module VeriFuzz.Verilog.Mutate + , module VeriFuzz.Verilog.Helpers + , module VeriFuzz.Verilog.Arbitrary ) where -import Test.VeriFuzz.Verilog.Arbitrary -import Test.VeriFuzz.Verilog.AST -import Test.VeriFuzz.Verilog.CodeGen -import Test.VeriFuzz.Verilog.Helpers -import Test.VeriFuzz.Verilog.Mutate +import VeriFuzz.Verilog.Arbitrary +import VeriFuzz.Verilog.AST +import VeriFuzz.Verilog.CodeGen +import VeriFuzz.Verilog.Helpers +import VeriFuzz.Verilog.Mutate diff --git a/src/VeriFuzz/Verilog/Arbitrary.hs b/src/VeriFuzz/Verilog/Arbitrary.hs index 1bcb727..075ad03 100644 --- a/src/VeriFuzz/Verilog/Arbitrary.hs +++ b/src/VeriFuzz/Verilog/Arbitrary.hs @@ -1,5 +1,5 @@ {-| -Module : Test.VeriFuzz.Verilog.Arbitrary +Module : VeriFuzz.Verilog.Arbitrary Description : Arbitrary instances for the AST. Copyright : (c) 2018-2019, Yann Herklotz Grave License : GPL-3 @@ -10,175 +10,61 @@ Portability : POSIX Arbitrary instances for the AST. -} -module Test.VeriFuzz.Verilog.Arbitrary where +module VeriFuzz.Verilog.Arbitrary where -import Control.Monad (replicateM) -import Data.Text (Text) -import qualified Data.Text as T -import qualified Test.QuickCheck as QC -import Test.VeriFuzz.Verilog.AST +import Control.Monad (replicateM) +import Data.Text (Text) +import qualified Data.Text as T +import qualified Test.QuickCheck as QC +import VeriFuzz.Verilog.AST -- Generate Arbitrary instances for the AST -positiveArb :: (QC.Arbitrary a, Ord a, Num a) => QC.Gen a -positiveArb = QC.suchThat QC.arbitrary (>0) - -expr :: Int -> QC.Gen Expr -expr 0 = QC.oneof - [ Id <$> QC.arbitrary - , Number <$> positiveArb <*> QC.arbitrary - , UnOp <$> QC.arbitrary <*> QC.arbitrary - -- , Str <$> QC.arbitrary - ] -expr n - | n > 0 = QC.oneof - [ Id <$> QC.arbitrary - , Number <$> positiveArb <*> QC.arbitrary - , Concat <$> QC.listOf1 (subexpr 4) - , UnOp <$> QC.arbitrary <*> QC.arbitrary - -- , Str <$> QC.arbitrary - , BinOp <$> subexpr 2 <*> QC.arbitrary <*> subexpr 2 - , Cond <$> subexpr 3 <*> subexpr 3 <*> subexpr 3 - ] - | otherwise = expr 0 - where - subexpr y = expr (n `div` y) - -statement :: Int -> QC.Gen Stmnt -statement 0 = QC.oneof - [ BlockAssign <$> QC.arbitrary - , NonBlockAssign <$> QC.arbitrary - -- , StatCA <$> QC.arbitrary - , TaskEnable <$> QC.arbitrary - , SysTaskEnable <$> QC.arbitrary - ] -statement n - | n > 0 = QC.oneof - [ TimeCtrl <$> QC.arbitrary <*> (Just <$> substat 2) - , SeqBlock <$> QC.listOf1 (substat 4) - , BlockAssign <$> QC.arbitrary - , NonBlockAssign <$> QC.arbitrary - -- , StatCA <$> QC.arbitrary - , TaskEnable <$> QC.arbitrary - , SysTaskEnable <$> QC.arbitrary - ] - | otherwise = statement 0 - where - substat y = statement (n `div` y) - -modPortGen :: QC.Gen Port -modPortGen = QC.oneof - [ Port Wire <$> positiveArb <*> QC.arbitrary - , Port <$> (Reg <$> QC.arbitrary) <*> positiveArb <*> QC.arbitrary - ] - -instance QC.Arbitrary Text where - arbitrary = T.pack <$> QC.arbitrary - -instance QC.Arbitrary Identifier where - arbitrary = do - l <- QC.choose (2, 10) - Identifier . T.pack <$> replicateM l (QC.elements ['a'..'z']) - -instance QC.Arbitrary BinaryOperator where - arbitrary = QC.elements - [ BinPlus - , BinMinus - , BinTimes - , BinDiv - , BinMod - , BinEq - , BinNEq - , BinCEq - , BinCNEq - , BinLAnd - , BinLOr - , BinLT - , BinLEq - , BinGT - , BinGEq - , BinAnd - , BinOr - , BinXor - , BinXNor - , BinXNorInv - , BinPower - , BinLSL - , BinLSR - , BinASL - , BinASR - ] - -instance QC.Arbitrary UnaryOperator where - arbitrary = QC.elements - [ UnPlus - , UnMinus - , UnNot - , UnAnd - , UnNand - , UnOr - , UnNor - , UnXor - , UnNxor - , UnNxorInv - ] - -instance QC.Arbitrary PortDir where - arbitrary = QC.elements [PortIn, PortOut, PortInOut] - -instance QC.Arbitrary PortType where - arbitrary = QC.oneof [pure Wire, Reg <$> QC.arbitrary] - -instance QC.Arbitrary Port where - arbitrary = Port <$> QC.arbitrary <*> positiveArb <*> QC.arbitrary - -instance QC.Arbitrary Delay where - arbitrary = Delay <$> positiveArb - -instance QC.Arbitrary Event where - arbitrary = EId <$> QC.arbitrary - -instance QC.Arbitrary ModConn where - arbitrary = ModConn <$> QC.arbitrary - -instance QC.Arbitrary ConstExpr where - arbitrary = ConstExpr <$> positiveArb - -instance QC.Arbitrary LVal where - arbitrary = QC.oneof [ RegId <$> QC.arbitrary - , RegExpr <$> QC.arbitrary <*> QC.arbitrary - , RegSize <$> QC.arbitrary <*> QC.arbitrary <*> QC.arbitrary - ] - -instance QC.Arbitrary Assign where - arbitrary = Assign <$> QC.arbitrary <*> QC.arbitrary <*> QC.arbitrary - -instance QC.Arbitrary Expr where - arbitrary = QC.sized expr - -instance QC.Arbitrary Stmnt where - arbitrary = QC.sized statement - -instance QC.Arbitrary ContAssign where - arbitrary = ContAssign <$> QC.arbitrary <*> QC.arbitrary - -instance QC.Arbitrary Task where - arbitrary = Task <$> QC.arbitrary <*> QC.arbitrary - -instance QC.Arbitrary ModItem where - arbitrary = QC.oneof [ ModCA <$> QC.arbitrary - , ModInst <$> QC.arbitrary <*> QC.arbitrary <*> QC.arbitrary - , Initial <$> QC.arbitrary - , Always <$> (EventCtrl <$> QC.arbitrary <*> QC.arbitrary) - , Decl <$> pure Nothing <*> QC.arbitrary - ] - -instance QC.Arbitrary ModDecl where - arbitrary = ModDecl <$> QC.arbitrary <*> QC.arbitrary - <*> QC.listOf1 modPortGen <*> QC.arbitrary - -instance QC.Arbitrary Description where - arbitrary = Description <$> QC.arbitrary - -instance QC.Arbitrary VerilogSrc where - arbitrary = VerilogSrc <$> QC.arbitrary + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/test/Property.hs b/test/Property.hs index 8fc9020..80c6f68 100644 --- a/test/Property.hs +++ b/test/Property.hs @@ -4,8 +4,8 @@ import qualified Data.Graph.Inductive as G import Data.Graph.Inductive.PatriciaTree (Gr) import Test.Tasty import qualified Test.Tasty.QuickCheck as QC -import Test.VeriFuzz -import qualified Test.VeriFuzz.Graph.RandomAlt as V +import VeriFuzz +import qualified VeriFuzz.Graph.RandomAlt as V newtype TestGraph = TestGraph { getGraph :: Gr Gate () } deriving (Show) diff --git a/test/Test.hs b/test/Test.hs index 08a4799..389fdff 100644 --- a/test/Test.hs +++ b/test/Test.hs @@ -2,8 +2,8 @@ module Main where import Property import Test.Tasty -import Test.VeriFuzz import Unit +import VeriFuzz tests :: TestTree tests = testGroup "Tests" [unitTests, propertyTests] diff --git a/test/Unit.hs b/test/Unit.hs index 13b9027..8bcc702 100644 --- a/test/Unit.hs +++ b/test/Unit.hs @@ -6,7 +6,7 @@ import Data.Text (Text) import qualified Data.Text as T import Test.Tasty import Test.Tasty.HUnit -import Test.VeriFuzz +import VeriFuzz unitTests = testGroup "Unit tests" [ testCase "Transformation of AST" $ diff --git a/verifuzz.cabal b/verifuzz.cabal index f2524d8..bd06eef 100644 --- a/verifuzz.cabal +++ b/verifuzz.cabal @@ -17,25 +17,25 @@ extra-source-files: README.md library hs-source-dirs: src default-language: Haskell2010 - other-modules: Test.VeriFuzz.Internal.Shared - , Test.VeriFuzz.Internal.Gen - exposed-modules: Test.VeriFuzz - , Test.VeriFuzz.Circuit - , Test.VeriFuzz.Graph.ASTGen - , Test.VeriFuzz.Graph.CodeGen - , Test.VeriFuzz.Graph.Random - , Test.VeriFuzz.Graph.RandomAlt - , Test.VeriFuzz.Simulator - , Test.VeriFuzz.Simulator.General - , Test.VeriFuzz.Simulator.Icarus - , Test.VeriFuzz.Simulator.Xst - , Test.VeriFuzz.Simulator.Yosys - , Test.VeriFuzz.Verilog - , Test.VeriFuzz.Verilog.AST - , Test.VeriFuzz.Verilog.Arbitrary - , Test.VeriFuzz.Verilog.CodeGen - , Test.VeriFuzz.Verilog.Helpers - , Test.VeriFuzz.Verilog.Mutate + other-modules: VeriFuzz.Internal.Shared + , VeriFuzz.Internal.Gen + exposed-modules: VeriFuzz + , VeriFuzz.Circuit + , VeriFuzz.Graph.ASTGen + , VeriFuzz.Graph.CodeGen + , VeriFuzz.Graph.Random + , VeriFuzz.Graph.RandomAlt + , VeriFuzz.Simulator + , VeriFuzz.Simulator.General + , VeriFuzz.Simulator.Icarus + , VeriFuzz.Simulator.Xst + , VeriFuzz.Simulator.Yosys + , VeriFuzz.Verilog + , VeriFuzz.Verilog.AST + , VeriFuzz.Verilog.Arbitrary + , VeriFuzz.Verilog.CodeGen + , VeriFuzz.Verilog.Helpers + , VeriFuzz.Verilog.Mutate build-depends: base >= 4.7 && < 5 , QuickCheck >=2.3 && <2.10 , fgl |