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-rw-r--r--app/Main.hs11
-rw-r--r--src/VeriFuzz/AST.hs2
-rw-r--r--src/VeriFuzz/General.hs10
-rw-r--r--src/VeriFuzz/Icarus.hs2
-rw-r--r--src/VeriFuzz/XST.hs12
-rw-r--r--src/VeriFuzz/Yosys.hs20
6 files changed, 35 insertions, 22 deletions
diff --git a/app/Main.hs b/app/Main.hs
index 107eef5..fa4f4f4 100644
--- a/app/Main.hs
+++ b/app/Main.hs
@@ -53,7 +53,7 @@ runSimulation = do
onFailure :: Text -> RunFailed -> Sh ()
onFailure t _ = do
- echoP "FAIL"
+ echoP "Test FAIL"
cd ".."
cp_r (fromText t) $ fromText (t <> "_failed")
@@ -61,14 +61,13 @@ runEquivalence :: Gen ModDecl -> Text -> Int -> IO ()
runEquivalence gm t i = do
m <- QC.generate gm
shellyFailDir $ do
- mkdir_p (fromText "equiv" </> fromText n)
+ mkdir_p (fromText "output" </> fromText n)
curr <- toTextIgnore <$> pwd
setenv "VERIFUZZ_ROOT" curr
- cd (fromText "equiv" </> fromText n)
+ cd (fromText "output" </> fromText n)
catch_sh (runEquiv defaultYosys defaultYosys
- (Just defaultXst) m >> echoP "OK") $
+ (Just defaultXst) m >> echoP "Test OK") $
onFailure n
- cd ".."
when (i < 5) (runEquivalence gm t $ i+1)
where
n = t <> "_" <> T.pack (show i)
@@ -78,5 +77,5 @@ main :: IO ()
main = do
num <- getNumCapabilities
vars <- sequence $ (\x -> myForkIO $
- runEquivalence (randomMod 5 50) ("test_" <> T.pack (show x)) 0) <$> [1..num]
+ runEquivalence (randomMod 5 15) ("test_" <> T.pack (show x)) 0) <$> [1..num]
sequence_ $ takeMVar <$> vars
diff --git a/src/VeriFuzz/AST.hs b/src/VeriFuzz/AST.hs
index 259da50..15fa792 100644
--- a/src/VeriFuzz/AST.hs
+++ b/src/VeriFuzz/AST.hs
@@ -207,7 +207,7 @@ instance QC.Arbitrary BinaryOperator where
, BinXor
, BinXNor
, BinXNorInv
- , BinPower
+-- , BinPower
, BinLSL
, BinLSR
, BinASL
diff --git a/src/VeriFuzz/General.hs b/src/VeriFuzz/General.hs
index 1d2f183..37a8f90 100644
--- a/src/VeriFuzz/General.hs
+++ b/src/VeriFuzz/General.hs
@@ -46,11 +46,11 @@ rootPath = do
maybe current fromText <$> get_env "VERIFUZZ_ROOT"
timeout :: FilePath -> [Text] -> Sh Text
-timeout = command1 "timeout" ["180"] . toTextIgnore
+timeout = command1 "timeout" ["500"] . toTextIgnore
{-# INLINE timeout #-}
timeout_ :: FilePath -> [Text] -> Sh ()
-timeout_ = command1_ "timeout" ["180"] . toTextIgnore
+timeout_ = command1_ "timeout" ["500"] . toTextIgnore
{-# INLINE timeout_ #-}
-- | Helper function to convert bytestrings to integers
@@ -68,3 +68,9 @@ echoP t = do
echo $ bname fn <> " :: " <> t
where
bname = T.pack . takeBaseName . T.unpack . toTextIgnore
+
+logger :: FilePath -> Text -> Sh a -> Sh a
+logger fp name =
+ log_stderr_with (l "_log.stderr.txt") . log_stdout_with (l "_log.txt")
+ where
+ l s = writeFile (T.unpack (toTextIgnore $ fp </> fromText name) <> s) . T.unpack
diff --git a/src/VeriFuzz/Icarus.hs b/src/VeriFuzz/Icarus.hs
index 8aa4698..ff389a4 100644
--- a/src/VeriFuzz/Icarus.hs
+++ b/src/VeriFuzz/Icarus.hs
@@ -62,5 +62,5 @@ runSimIcarus sim m bss = do
let modWithTb = VerilogSrc $ Description <$> [newtb, m]
writefile "main.v" $ genSource modWithTb
echoP "Run icarus"
- noPrint $ run_ (icarusPath sim) ["-o", "main", "main.v"]
+ run_ (icarusPath sim) ["-o", "main", "main.v"]
hash <$> run (vvpPath sim) ["main"]
diff --git a/src/VeriFuzz/XST.hs b/src/VeriFuzz/XST.hs
index 3d745fe..b72d975 100644
--- a/src/VeriFuzz/XST.hs
+++ b/src/VeriFuzz/XST.hs
@@ -39,16 +39,18 @@ defaultXst =
runSynthXst :: Xst -> ModDecl -> FilePath -> Sh ()
runSynthXst sim m outf = do
+ dir <- pwd
writefile xstFile $ xstSynthConfig m
writefile prjFile [st|verilog work "rtl.v"|]
writefile "rtl.v" $ genSource m
- echoP "Run xst"
- noPrint $ timeout_ (xstPath sim) ["-ifn", toTextIgnore xstFile]
- echoP "Run netgen"
- noPrint $ run_ (netgenPath sim)
+ echoP "XST: run"
+ _ <- logger dir "xst" $ timeout (xstPath sim) ["-ifn", toTextIgnore xstFile]
+ echoP "XST: netgen"
+ _ <- logger dir "netgen" $ run (netgenPath sim)
["-w", "-ofmt", "verilog", toTextIgnore $ modFile <.> "ngc", toTextIgnore outf]
- echoP "Clean synthesized file"
+ echoP "XST: clean"
noPrint $ run_ "sed" ["-i", "/^`ifndef/,/^`endif/ d; s/ *Timestamp: .*//;", toTextIgnore outf]
+ echoP "XST: done"
where
modFile = fromText $ modName m
xstFile = modFile <.> "xst"
diff --git a/src/VeriFuzz/Yosys.hs b/src/VeriFuzz/Yosys.hs
index 676e1b0..e64104a 100644
--- a/src/VeriFuzz/Yosys.hs
+++ b/src/VeriFuzz/Yosys.hs
@@ -32,7 +32,7 @@ instance Synthesize Yosys where
runSynth = runSynthYosys
defaultYosys :: Yosys
-defaultYosys = Yosys "/usr/bin/yosys"
+defaultYosys = Yosys "yosys"
writeSimFile
:: Yosys -- ^ Simulator instance
@@ -45,9 +45,11 @@ writeSimFile _ m file = do
runSynthYosys :: Yosys -> ModDecl -> FilePath -> Sh ()
runSynthYosys sim m outf = do
+ dir <- pwd
writefile inpf $ genSource m
- echoP "Run yosim"
- noPrint $ run_ (yosysPath sim) ["-q", "-b", "verilog -noattr", "-o", out, "-S", inp]
+ echoP "Yosys: synthesis"
+ _ <- logger dir "yosys" $ run (yosysPath sim) ["-q", "-b", "verilog -noattr", "-o", out, "-S", inp]
+ echoP "Yosys: synthesis done"
where
inpf = "rtl.v"
inp = toTextIgnore inpf
@@ -64,17 +66,21 @@ runEquivYosys yosys sim1 sim2 m = do
writefile checkFile $ yosysSatConfig sim1 sim2 m
runSynth sim1 m $ fromText [st|syn_#{toText sim1}.v|]
runMaybeSynth sim2 m
- echoP "Run yosys"
- noPrint $ run_ (yosysPath yosys) [toTextIgnore checkFile]
+ echoP "Yosys: equivalence check"
+ run_ (yosysPath yosys) [toTextIgnore checkFile]
+ echoP "Yosys: equivalence done"
where
checkFile = fromText [st|test.#{toText sim1}.#{maybe "rtl" toText sim2}.ys|]
runEquiv :: (Synthesize a, Synthesize b) => Yosys -> a -> Maybe b -> ModDecl -> Sh ()
runEquiv _ sim1 sim2 m = do
root <- rootPath
+ dir <- pwd
+ echoP "SymbiYosys: setup"
writefile "top.v" . genSource . initMod $ makeTopAssert m
writefile "test.sby" $ sbyConfig root sim1 sim2 m
runSynth sim1 m $ fromText [st|syn_#{toText sim1}.v|]
runMaybeSynth sim2 m
- echoP "Run SymbiYosys"
- noPrint $ run_ "sby" ["test.sby"]
+ echoP "SymbiYosys: run"
+ _ <- logger dir "symbiyosys" $ run "sby" ["test.sby"]
+ echoP "SymbiYosys: done"
generated by cgit (git 2.34.1) at 2024-06-28 21:35:13 +0000