diff options
| -rw-r--r-- | app/Main.hs | 13 | ||||
| -rw-r--r-- | src/VeriFuzz/Yosys.hs | 2 |
2 files changed, 11 insertions, 4 deletions
diff --git a/app/Main.hs b/app/Main.hs index 1979112..0557996 100644 --- a/app/Main.hs +++ b/app/Main.hs @@ -53,9 +53,16 @@ runSimulation = do onFailure :: Text -> RunFailed -> Sh () onFailure t _ = do - echoP "Test FAIL" - cd ".." - cp_r (fromText t) $ fromText (t <> "_failed") + ex <- lastExitCode + case ex of + 124 -> do + echoP "Test TIMEOUT" + cd ".." + cp_r (fromText t) $ fromText (t <> "_timeout") + _ -> do + echoP "Test FAIL" + cd ".." + cp_r (fromText t) $ fromText (t <> "_failed") runEquivalence :: Gen ModDecl -> Text -> Int -> IO () runEquivalence gm t i = do diff --git a/src/VeriFuzz/Yosys.hs b/src/VeriFuzz/Yosys.hs index e64104a..d7b0014 100644 --- a/src/VeriFuzz/Yosys.hs +++ b/src/VeriFuzz/Yosys.hs @@ -48,7 +48,7 @@ runSynthYosys sim m outf = do dir <- pwd writefile inpf $ genSource m echoP "Yosys: synthesis" - _ <- logger dir "yosys" $ run (yosysPath sim) ["-q", "-b", "verilog -noattr", "-o", out, "-S", inp] + _ <- logger dir "yosys" $ timeout (yosysPath sim) ["-q", "-b", "verilog -noattr", "-o", out, "-S", inp] echoP "Yosys: synthesis done" where inpf = "rtl.v" |