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-rw-r--r--src/VeriFuzz/Gen.hs11
1 files changed, 0 insertions, 11 deletions
diff --git a/src/VeriFuzz/Gen.hs b/src/VeriFuzz/Gen.hs
index 5c8a60b..8dbbe24 100644
--- a/src/VeriFuzz/Gen.hs
+++ b/src/VeriFuzz/Gen.hs
@@ -31,7 +31,6 @@ import Test.QuickCheck (Gen)
import qualified Test.QuickCheck as QC
import VeriFuzz.AST
import VeriFuzz.ASTGen
-import VeriFuzz.CodeGen
import VeriFuzz.Config
import VeriFuzz.Internal
import VeriFuzz.Mutate
@@ -126,16 +125,6 @@ scopedExpr = do
lvalFromPort :: Port -> LVal
lvalFromPort (Port _ _ _ i) = RegId i
-scopedReg :: StateGen LVal
-scopedReg = do
- context <- get
- gen
- . QC.elements
- . fmap lvalFromPort
- . filter (\p -> p ^. portType == Reg)
- $ context
- ^. variables
-
probability :: Config -> Probability
probability c = c ^. configProbability