diff options
| -rw-r--r-- | src/VeriFuzz/Verilog/Mutate.hs | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/VeriFuzz/Verilog/Mutate.hs b/src/VeriFuzz/Verilog/Mutate.hs index 69b6d57..eca472f 100644 --- a/src/VeriFuzz/Verilog/Mutate.hs +++ b/src/VeriFuzz/Verilog/Mutate.hs @@ -31,6 +31,7 @@ module VeriFuzz.Verilog.Mutate , simplify , removeId , combineAssigns + , combineAssigns_ , declareMod ) where @@ -270,3 +271,7 @@ combineAssigns :: Port -> [ModItem] -> [ModItem] combineAssigns p a = a <> [ModCA . ContAssign (p ^. portName) . fold $ Id <$> assigns] where assigns = a ^.. traverse . modContAssign . contAssignNetLVal + +combineAssigns_ :: Port -> [Port] -> ModItem +combineAssigns_ p ps = + ModCA . ContAssign (p ^. portName) . fold $ Id <$> ps ^.. traverse . portName |