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-rw-r--r--data/cells_xilinx_7.v17
1 files changed, 0 insertions, 17 deletions
diff --git a/data/cells_xilinx_7.v b/data/cells_xilinx_7.v
index cfd7578..560091d 100644
--- a/data/cells_xilinx_7.v
+++ b/data/cells_xilinx_7.v
@@ -214,12 +214,9 @@ endmodule
module LD (Q, D, G);
parameter INIT = 1'b0;
-
output Q;
wire Q;
-
input D, G;
-
reg q_out;
initial q_out = INIT;
@@ -230,25 +227,15 @@ module LD (Q, D, G);
if (G)
q_out <= D;
- specify
- if (G)
- (D +=> Q) = (100, 100);
- (posedge G => (Q +: D)) = (100, 100);
- endspecify
-
endmodule
module FD (Q, C, D);
-
parameter INIT = 1'b0;
-
output Q;
-
input C, D;
wire Q;
reg q_out;
- tri0 GSR = glbl.GSR;
initial q_out = INIT;
@@ -257,8 +244,4 @@ module FD (Q, C, D);
assign Q = q_out;
- specify
- (posedge C => (Q +: D)) = (100, 100);
- endspecify
-
endmodule