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| -rw-r--r-- | bugs/quartus_12.md | 19 |
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diff --git a/bugs/quartus_12.md b/bugs/quartus_12.md new file mode 100644 index 0000000..9d8b278 --- /dev/null +++ b/bugs/quartus_12.md @@ -0,0 +1,19 @@ +# Wrong Signed extension in binary expression + +[ Not fixed | N/a ] + +## Affected versions + +- Quartus 19.1 + +## Description + +Wrong signed extension in the binary xor operation. As the LHS in the binary operation is unsigned, the RHS should also be extended in an unsigned way, even though the `$signed` function is applied on the result. Therefore, the output should be `~ 2'b01 = 2'b10`, and not what Quartus does, which is `~ 2'b11 = 2'b00`. + +```verilog +module top(y, wire1); + output [1:0] y; + input wire1; + assign y = 2'b11 ^ $signed(wire1); +endmodule +``` |