diff options
| -rw-r--r-- | bugs/yosys_11.md | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/bugs/yosys_11.md b/bugs/yosys_11.md index 3247135..341155c 100644 --- a/bugs/yosys_11.md +++ b/bugs/yosys_11.md @@ -23,7 +23,7 @@ module top(y, clk); endmodule ``` -However, in Yosys 0.9 it is compiled to: +However, in Yosys 0.9 it is compiled to the following, which outputs a constant one after the first clock cycle: ```verilog /* Generated by Yosys 0.9 (git sha1 1979e0b1, clang 7.0.1-8 -fPIC -Os) */ |