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-rw-r--r--app/Main.hs12
1 files changed, 6 insertions, 6 deletions
diff --git a/app/Main.hs b/app/Main.hs
index 321b536..de3f870 100644
--- a/app/Main.hs
+++ b/app/Main.hs
@@ -12,12 +12,12 @@ instance Gviz.Labellable Gate where
toLabelValue gate = Gviz.StrLabel . T.pack $ show gate
main :: IO ()
---main = sample (arbitrary :: Gen (Circuit Input))
+ --main = sample (arbitrary :: Gen (Circuit Input))
main = do
- --gr <- genRandomDAG 100 :: IO (G.Gr Gate ())
--- _ <- runGraphviz (graphToDot quickParams $ emap (const "") gr) Png "output.png",
--- T.putStrLn $ generate gr
- g <- QC.generate (QC.arbitrary :: QC.Gen VerilogSrc)
- --render . genVerilogSrc . addTestBench . nestUpTo 20 . generateAST $ Circuit gr
+ --gr <- genRandomDAG 100 :: IO (G.Gr Gate ())
+ -- _ <- runGraphviz (graphToDot quickParams $ emap (const "") gr) Png "output.png",
+ -- T.putStrLn $ generate gr
+ g <- QC.generate (QC.resize 5 (QC.arbitrary :: QC.Gen VerilogSrc))
+ --render . genVerilogSrc . addTestBench . nestUpTo 20 . generateAST $ Circuit gr
render . genVerilogSrc . addTestBench $ g