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-rw-r--r--app/Main.hs5
1 files changed, 4 insertions, 1 deletions
diff --git a/app/Main.hs b/app/Main.hs
index c13d4c2..aeda625 100644
--- a/app/Main.hs
+++ b/app/Main.hs
@@ -43,7 +43,10 @@ runEquivalence t = do
^.. getVerilogSrc
. traverse
. getDescription
- shelly . chdir_p (fromText "equiv" </> fromText t) . verbosely $ runEquiv defaultYosys defaultYosys (Just defaultXst) circ
+ shelly . chdir_p (fromText "equiv" </> fromText t) . verbosely $ runEquiv defaultYosys
+ defaultYosys
+ (Just defaultXst)
+ circ
main :: IO ()
--main = sample (arbitrary :: Gen (Circuit Input))