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Diffstat (limited to 'app')
| -rw-r--r-- | app/Test.hs (renamed from app/Yosys.hs) | 0 |
1 files changed, 0 insertions, 0 deletions
diff --git a/app/Yosys.hs b/app/Test.hs index c67852c..c67852c 100644 --- a/app/Yosys.hs +++ b/app/Test.hs |
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index : verismith | |
| Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog. |
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